A storage device is provided which shares a host memory with a host. The storage device includes an interface that exchanges data with the host and implements a protocol to use a partial area of the host memory as a buffer of the storage device. A storage controller of the storage device monitors deterioration information of a first area of the buffer and transmits a corruption prediction notification associated with the first area to the host based on a result of the monitoring.

Systems and methods including one or more processors and one or more non-transitory computer readable storage devices storing computing instructions configured to run on the one or more processing modules and perform: gathering first data comprising first interactions of a user with a first graphical user interface; storing the first data comprising the first interactions of the user with the first graphical user interface as at least one first vector by adding to the at least one first vector for each level of a hierarchical categorization of the first user interface; gathering second data comprising second interactions of the user with a second graphical user interface; storing the second data comprising the second interactions of the user with the second graphical user interface as at least one second vector; determining an intent of the user using the at least one first vector, the at least one second vector, and a predictive algorithm; and transmitting instructions to display a third graphical user interface for the user based upon the intent of the user. Other embodiments are disclosed herein.

Systems, apparatuses, and methods for implementing telemetry push aggregation techniques are described. A computing system includes one or more input/output (I/O) agents interposed between functional units and a communication fabric. A given I/O agent receives a set of aggregation rules from a power management unit. The I/O agent monitors traffic from the functional units, and the I/O agent generates telemetry data from the traffic data based on the set of aggregation rules. The telemetry data is used by the power management unit to make adjustments to one or more power settings.

A method of performing a full data reconstruction in a redundant array of independent disks (RAID) system with a protection pool of storage units includes determining that a physical disk of a storage cluster has been removed from service. The physical disk includes a set of physical extents and at least one physical extent of the set of physical extents is associated with an array of physical extents distributed across physical disks of the storage cluster. The method further includes transmitting a message to of the physical disks, to allocate replacement physical extents and assign the replacement physical extents to the array of physical extents and initiating reconstruction of data from the set of physical extents of the physical disk to the replacement physical extents.

System and method for aggressive credit waiting in a high performance computing environment. In accordance with an embodiment, systems and methods can provide for an indexed matrix of credit wait policies between ports within a single switch. In addition, systems and methods can provide for an array of credit wait polices at an egress port from a switch, the array being indexed by virtual lane.

The present disclosure relates to systems and methods for operation retry. The system may determine whether a retry is allowed for a target operation based on a retry strategy included in a retry proxy component. In response to determining that the retry is allowed for the target operation, the system may execute the target operation. The system may detect whether there is an exception associated with the execution of the target operation. In response to determining that there is the exception associated with the execution of the target operation, the system may determine whether a retry is needed for the target operation based on the retry strategy. In response to determining that the retry is unneeded for the target operation, the system may stop the target operation.

Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.

Systems and methods herein secure computer memory from potential hacks. In one embodiment, a system includes a computer memory, and a memory protection module communicatively coupled to the computer memory. The memory protection module is operable to assign a counter value to a write Input/Output (I/O) request, to encrypt data of the write I/O request based on the counter value, and to write the encrypted data to a location of the computer memory. The counter value comprises a version number of the write I/O request and, for example, the location of the computer memory to where the data of the write I/O request is being written in the computer memory. The memory protection module is further operable to compute the version number based on memory access patterns of an application writing to the computer memory.

A method includes asserting a field of an event flag mask register configured to inhibit an event handler. The method also includes, responsive to an event that corresponds to the field of the event flag mask register being triggered: asserting a field of an event flag register associated with the event; and based the field in the event flag register being asserted, taking an action by a task being executed by the data processor core.

According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.