Examples of systems and method described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.

Techniques for cache management involve: determining respective elimination scores of a plurality of entries in a cache based at least in part on compression rates of data blocks corresponding to the plurality of entries, the elimination score being proportional to the compression rate; and removing, from the cache, at least one entry with a relatively low elimination score among the plurality of entries. Such techniques are able to optimize the retention and elimination strategies for entries in a cache, thus increasing payoffs for using the cache.

A host for managing a storage device is provided. The host includes a storage host interface configured to communicate with the storage device comprising a cache and a non-volatile memory and at least one processor. The at least one processor may be configured to receive information indicating cache loss from the storage device after device reset of the storage device, suspend a data input/output operation for the storage device, transmit a buffer read command to the storage device, and receive cache information related to data remaining in the cache without being stored in the non-volatile memory before the device reset from the storage device in response to the buffer read command.

A method, computer program product, and computer system for receiving, by a computing device, a snapshot create operation of a volume to create a first snapshot. Existing dirty data of the volume for the first snapshot may be flushed from an in-memory cache. New writes to the volume for the first snapshot may be maintained in the in-memory cache as dirty. A snapshot create operation to the volume may be received to create a second snapshot. The new writes to the volume for the first snapshot may be combined as part of the second snapshot.

Systems, apparatuses, and methods related to a write-back cache policy to limit data transfer time to a memory device are described. A controller can orchestrate performance of operations to write data to a cache according to a write-back policy and write addresses associated with the data to a buffer. The controller can further orchestrate performance of operations to limit an amount of data stored by the buffer and/or a quantity of addresses stored in the buffer. In response to a power failure, the controller can cause the data stored in the cache to be flushed to a persistent memory device in communication with the cache.

A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.

A method, computer program product, and computing system for assigning a plurality of unique sequential identifiers to a plurality of tablets in a cache memory system. One or more metadata deltas associated with a metadata page stored in a storage array may be written to the plurality of tablets in the cache memory system. Each metadata delta stored in at least one tablet of the plurality of tablets may be written to the metadata page stored in the storage array, thus defining one or more destage tablets. A largest unique sequential identifier from the plurality of unique sequential identifiers assigned to the one or more destage tablets, may be written to the storage array, thus defining a current tablet identifier for the metadata page.

Methods and systems for memory cache entry replacement with pinned cache entries. Data structures are maintained for tracking a state of entries of a memory cache. A first data structure includes identifiers for pinned entries of a memory cache. A second data structure includes identifiers for unpinned entries of the memory cache that have been accessed once. A third data structure includes identifiers for unpinned entries of the memory cache that have been accessed more than once. A request to pin an entry is received. A determination is made that an identifier associated with the entry to pin is included in the second data structure or the third data structure. The identifier associated with the pinned entry is added to the first data structure. A detection is made at a time period that one or more entries of the memory cache are to be removed from the memory cache in accordance with an eviction protocol. Identifiers of one or more unpinned entries with state data that satisfies an eviction criterion associated with the eviction protocol are selected from the second data structure and/or the third data structure. The one or more unpinned entries are removed from the memory cache while the pinned entry with corresponding state data is maintained in the memory cache.

Methods, systems, and devices for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.

Managing data stored in a cache using a reinforcement learning agent may include: determining a set of current state observations with respect to a cache, wherein the set of current state observations is determined based on historical cache accesses to the cache; inputting the set of current state observations into an actor network of a reinforcement learning (RL) agent to obtain an action output by the actor network, wherein the RL agent is configured to manage data stored at the cache; inputting the set of current state observations and the action into a critic network of the RL agent to obtain a score corresponding to the action from the critic network; causing the RL agent to perform the action with respect to managing the data stored at the cache; using the score to update the actor network; and using a reward corresponding to the action to update the critic network.