An image processing method is provided, which is applied to a deep learning model. A cache queue is provided in front of each layer of the deep learning model; a plurality of computation tasks are preset for each layer of the deep learning model in advance, and are configured for computing weight parameters and corresponding to-be-processed data in a plurality of channels in each corresponding layer in parallel, and storing a computation result into a cache queue behind the corresponding layer thereof; in addition, as long as the cache queue in front of the layer includes the computation result stored in the previous layer, the layer can obtain the to-be-processed data from the computation result, subsequent computation is performed, and a parallel pipeline computation mode is also formed between the layers. By means of the mode, the throughput rate during image processing is remarkably improved, and the image processing parallelism degree and speed and the computation performance of the deep learning model are improved. Further provided are an image processing device and system, which have the same beneficial effects as the above image processing method.

An integrated circuit and a method for executing a cache management operation are provided. The integrated circuit includes a master interface, a slave interface, and a link. The link is connected between the master interface and the slave interface, and the link includes an A-channel, a B-channel, a C-channel, a D-channel, and an E-channel. The A-channel is configured to transmit a cache management operation message of the master interface to the slave interface, and the cache management operation message is configured to manage data consistency between different data caches. The D-channel is configured to transmit a cache management operation acknowledgement message of the slave interface to the master interface.

Disclosed herein are an apparatus and method for managing cache memory. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program reads an s1-tag and an s2-tag of cache memory upon receiving an access request address for reading data in response to a request to access the cache memory, checks whether the access request address matches the value of the s1-tag and the value of the s2-tag, and reads the data from data memory when the access request address matches all of the value of the s1-tag and the value of the s2-tag.

A data operation method of a memory system is provided. The method includes, based on an obtained logical to physical mapping table, determining whether address values of a plurality of target physical addresses in the logical to physical mapping table corresponding to a plurality of target logical addresses are continuous; if so, selecting one of the plurality of target physical addresses as a base physical address, and setting a base physical address offset based on address values of remaining target physical addresses; and storing the base physical address and the base physical address offset into a cache of a memory controller, as a mapping relationship of the plurality of target logical addresses corresponding to the plurality of target physical addresses.

A variety of applications can include a memory device having a memory die designed to control a power budget for a cache and a memory array of the memory die. A first flag received from a data path identifies a start of a cache operation on the data and a second flag from the data path identifies an end of the cache operation. A controller for peak power management can be implemented to control the power budget based on determination of usage of current associated with the cache from the first and second flags. In various embodiments, the controller can be operable to feedback a signal to a memory controller external to the memory die to adjust an operating speed of an interface from the memory controller to the memory die. Additional devices, systems, and methods are discussed.

Control logic in a memory device initiates an express programming operation to program the set of memory cells to a target programming level of a set of programming levels. A set of data associated with the express programming operation is stored in a cache register. At a first time during the execution of the express programming operation, a prediction operation is executed to determine a prediction result corresponding to a programming status of the set of memory cells. The prediction result is compared to a threshold level to determine whether a condition is satisfied. The release of the set of data from the cache register is caused in response to satisfying the condition.

An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on the first data. The processor instructs the cache controller to store a second data in the cache line in the cache causing eviction of the first data from the cache line. The processor compares based on the tagging the first data and the second data and suppresses modification of the cache line based on the comparing of the first data and the second data.

A server in a cloud-based environment interfaces with storage devices that store shared content accessible by two or more users. Individual items within the shared content are associated with respective object metadata that is also stored in the cloud-based environment. Download requests initiate downloads of instances of a virtual file system module to two or more user devices associated with two or more users. The downloaded virtual file system modules capture local metadata that pertains to local object operations directed by the users over the shared content. Changed object metadata attributes are delivered to the server and to other user devices that are accessing the shared content. Peer-to-peer connections can be established between the two or more user devices. Object can be divided into smaller portions such that processing the individual smaller portions of a larger object reduces the likelihood of a conflict between user operations over the shared content.

Described are methods, systems and computer readable media for providing a current row position query language construct and array processing query language constructs and associated processing.