A vehicle agnostic removable pod can be mounted on a vehicle using one or more legs of a pod mount. The removable pod can collect and time stamp a variety of environmental data as well as vehicle data. For example, environmental data can be collected using a sensor suite which can include an IMU, 3D positioning sensor, one or more cameras, and/or a LIDAR unit. As another example, vehicle data can be collected via a CAN bus attached to the vehicle. Environmental data and/or vehicle data can be time stamped and transmitted to a remote server for further processing by a computing device.

A parallel-to-serial interface circuit includes an equalizer to delay odd data by a half period and sequentially generate odd pre data, odd main data, and odd post data, and delay even data by a half period and sequentially generate even pre data, even main data, and even post data, a final parallel-to-serial converter to sequentially and alternately select the even pre data and the odd pre data to generate pre data, sequentially and alternately select inverted odd main data and inverted even main data to generate inverted main data, and sequentially and alternately select the even post data and the odd post data to generate post data, and a driver to drive the pre data to generate a pre data level, drive the inverted main data to generate an inverted main data level, and drive the post data to generate a post data level.

The present invention relates to an optical biometric sensor comprising: a read-out circuitry controllable for converting analog sensing signals to digital signals, the analog sensing signals being indicative of an image acquired by an image sensor comprising an array of photodetectors; and a timing circuitry configured to control the read-out circuitry to provide digital signals based on a present data transfer capacity on a data transfer bus configured to transfer data indicative of the digital signals from the optical biometric sensor to a host device.

A serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof are provided. A SPI architecture includes a master IC and a slave IC. When the SPI IC is a master IC, the SPI IC generates first command information for a slave IC, generates first debugging information corresponding to the first command information, and sends the first command information and the first debugging information to the slave IC through a SPI channel. When the SPI IC is the slave IC, the SPI IC receives second command information and second debugging information sent by the master IC through the SPI channel and checks the second command information by using the second debugging information. When the SPI IC is a target slave circuit selected by the master IC, the SPI IC executes the second command information under a condition that the second command information is checked and is correct.

A system comprises an interposer including interconnect and multiple chiplets arranged on the interposer. Each chiplet includes multiple chiplet input-output (I/O) channels interconnected to I/O channels of other chiplets by the interposer; a chiplet I/O interface for the chiplet I/O channels that includes multiple interface layers; and initialization logic circuitry configured to advance initialization of the chiplet interface sequentially through the interface layers starting with a lowest interface layer.

A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to use information on a data input port or data input bus to determine a communication status of one or multiple secondary devices on the bus.

A memory system for storing and retrieving data may include a controller, a first switch, a second switch connected to the first switch via an interconnecting bus, and a plurality of memory devices. The controller may have a first serial interface. The first switch may have one or more serial interfaces and one or more memory ports. The first serial interface of the controller may be communicatively connected to a first serial interface of the one or more serial interfaces of the first switch via a first serial bus. Each of the one or more memory ports of the first switch may be communicatively connected to a subset of the plurality of memory devices via a memory bus. The first switch may transfer data between the controller and the subsets of the plurality of memory devices via the one or more memory ports.

A vehicle agnostic removable pod can be mounted on a vehicle using one or more legs of a pod mount. The removable pod can collect and time stamp a variety of environmental data as well as vehicle data. For example, environmental data can be collected using a sensor suite which can include an IMU, 3D positioning sensor, one or more cameras, and/or a LIDAR unit. As another example, vehicle data can be collected via a CAN bus attached to the vehicle. Environmental data and/or vehicle data can be time stamped and transmitted to a remote server for further processing by a computing device.

Techniques are disclosed for systems and methods associated with a modular electrical power distribution system with module detection. A modular electrical power distribution system may include a plurality of controllers, a shared serial communication bus between the plurality of controllers, and a module detection signal line coupled through the plurality of controllers. The plurality of controllers may include a master controller, a power input controller, and one or more load controllers disposed between the master controller and the power input controller.

Methods and systems for data communication using the single wire communication protocol and the universal asynchronous receiver-transmitter (UART) communication protocol are disclosed. The method includes receiving by a first device a reset pulse. The method includes operating the first device in a standard speed single wire protocol if the width of the reset pulse is between 480 and 640 micro seconds. The method includes operating the first device in an overdrive speed single wire protocol if the width of the reset pulse is between 48 and 80 micro seconds. The method includes operating the first device in a universal asynchronous receiver-transmitter (UART) protocol if the width of the reset pulse is between 240 and 480 micro seconds. The method includes transmitting by the first device an answer responsive to the reset pulse. The method includes synchronizing the first device with a host device responsive to the reset pulse.