A single communication interface between a master device and at least one slave device and a method with internal/external addressing mode using the single communication interface. In the single communication interface between a master device and at least one slave device, the master device includes a master interface and the slave device comprises a slave interface and a slave bus-system, whereas the slave interface is directly connected to the slave bus-system, wherein the master interface and the slave interface communicate on a packet based protocol by an internal and external addressing mode inside the slave interface, whereas the addressing mode, data transfer direction and data address location are coded by the packet based protocol inside a first 32-bit word of each transmission between the master device and slave device over the single communication interface.

A multi-die and multi-core computing platform in which multiple dies share the same storage device for firmware code storage is shown. After a slave die loads #1 firmware code from the storage device through a bus, the right to use the bus is released by the slave die and the slave die outputs a #0 enable signal to a master die. According to the #0 enable signal, the master die gains the right to use the bus. Through the bus, the master die loads #0 firmware code from the storage device. The slave die executes the #1 firmware code and the master die executes the #0 firmware code to initialize a link between the master and slave dies.

A vehicle agnostic removable pod can be mounted on a vehicle using one or more legs of a pod mount. The removable pod can collect and time stamp a variety of environmental data as well as vehicle data. For example, environmental data can be collected using a sensor suite which can include an IMU, 3D positioning sensor, one or more cameras, and/or a LIDAR unit. As another example, vehicle data can be collected via a CAN bus attached to the vehicle. Environmental data and/or vehicle data can be time stamped and transmitted to a remote server for further processing by a computing device.

A system for camera serial interface lane implementation between camera sensor and host processor is disclosed. An input data receiving unit receives first input signal from a first camera sensor in at least one of a two-lane camera serial interface configuration (CSI) or a four-lane CSI configuration; receives second input signal from a second camera sensor in the two-lane CSI. A data selector device selecting a first port for forwarding input signal when the first input signal is received in the two-lane CSI, selecting a second port for forwarding the input signal when the first input signal is obtained in the four-lane CSI configuration. A host processor block including a first receiver block to generate a first output signal when the first input signal is received from the first port, a second receiver block generates a second output signal when the first input signal is obtained from the second port.

A method of transmitting data and command through an RS232 serial port incorporated with a user-end device and a server-end device connected through the RS232 serial port is disclosed and includes following steps: accumulating a value of a first counter of the user-end device and a value of a second counter of the server-end device whenever a data is transmitted from the server-end device to the user-end device; controlling the server-end device to stop transmitting the data and to wait when both of the two values reach a triggering threshold; controlling the user-end device to transmit a control command to the server-end device through the RS232 serial port while the server-end device is waiting; and, resetting the first and the second counter and controlling the server-end device to restore to transmit the data to the user-end device after a waiting time is elapsed.

An endpoint interface device architecture utilized in multi-drop communication networks, such as the RS485 architecture, that utilizes control logic software/firmware within the endpoint microprocessor to isolate shorted lines from the communication transceiver, and to communicate status information to a first or second data source.

A microcontroller is provided with a plurality of slave drive units for driving peripheral devices. Individual speed units are provided that have serial shift registers, multiplexors, and duplex data communication connections with individual serial registers of respective slave drive units of a series chain. In a first cycle or mode, a serial data connection between the serial shift registers of the speed units causes data to be serially communicated, at a first relatively faster pulse rate, from the microcontroller into the data input of the series chain and to the microcontroller from the data output of the series chain. In a second cycle or mode, for each pair of single speed unit and slave drive unit, the duplex data communication between the serial shift registers of the pair causes, at a second relatively slower pulse rate, data to be serially communicated in parallel therebetween.

Disclosed are techniques for using firmware and hardware blocks of a device to decode signals encoded by signal edge positioning within a data bit width, such as bi-phase mark space coding (BMC) used for encoding in-band communication of wireless charging systems. The first device may use general purpose I/O (GPIO) interrupts to detect the start of a packet. The firmware may synchronize and configure the clock of a serial peripheral interface (SPI) to oversample the signals. The SPI may store the sampled data into a buffer, freeing the firmware from having to expend processing cycles to detect the transitions of the data in real-time. The firmware may read the buffered samples to decode the packet data in a post-processing stage. The firmware may detect the end of the packet by polling and GPIO interrupts or based on the samples read from the buffer to stop the clock of the SPI.

Enhanced techniques for communicating with an integrated circuit chip card are disclosed. An integrated circuit chip card may include a processor, a memory storing a plurality applications executable by the processor, an input/output (I/O) interface, and a network interface coupled to the (I/O) interface. The network interface may implement a plurality of logical ports, and the network interface can be configurable to select between multiple communication protocols to communicate with an external device in a socket communication mode. The network interface can be configured to establish a plurality of communication channels between the external device the integrated circuit chip card using the plurality of logical ports, and each of the communication channels may support communication with one of the plurality of applications.

Enhanced techniques for communicating with an integrated circuit chip card are disclosed. An integrated circuit chip card may include a processor, a memory storing a plurality applications executable by the processor, an input/output (I/O) interface, and a network interface coupled to the (I/O) interface. The network interface may implement a plurality of logical ports, and the network interface can be configurable to select between multiple communication protocols to communicate with an external device in a socket communication mode. The network interface can be configured to establish a plurality of communication channels between the external device the integrated circuit chip card using the plurality of logical ports, and each of the communication channels may support communication with one of the plurality of applications.