Patent classifications
G06F2213/0002
Operation device
An operation device includes a transmission interface and a control circuit. The transmission interface is coupled to the bus. The control circuit outputs a switching command to the first slave device at the first transmission rate and via the transmission interface, to control the first slave device to operate in an update mode, and outputs update data to the first slave device at the second transmission rate and via the transmission interface, so as to update a program code of the first slave device. The second transmission rate is higher than the first transmission rate.
CRYPTOCURRENCY MINER AND DEVICE ENUMERATION
A cryptocurrency miner includes a serial bus, compute modules, and a controller. Each compute module includes upstream ports, downstream ports, a pass-through buffer coupling the upstream ports to the downstream ports, and a serial bus interface coupled to the serial bus via the first upstream ports and the first downstream ports. The controller controls operation of the compute modules via commands on the serial bus. The serial bus includes bus segments between respective upstream and downstream ports of the compute modules.
Arrangement and method for updating a control software in a high-voltage control unit
An arrangement and a method for updating a control software in a high-voltage control device, has as its objective to specify a solution with which an update of the control software, independently of a current operational state of the high-voltage region of the high-voltage control device, is enabled for the low voltage region as well as also the high-voltage region of the high-voltage control device.
Detection apparatus and method
Embodiments of application relate to the field of communications technologies, and in particular, to a detection apparatus and method for quickly locating a wire fault of a serial bus and finding a cause. The apparatus is connected to a serial bus between a primary device and a secondary device, the serial bus includes a first bus and a second bus, and the apparatus includes a voltage divider module, a voltage follower module, a forward bias module, and a control module that are sequentially connected. The voltage divider module is configured to reduce a voltage of the first bus and a voltage of the second bus. The voltage follower module is configured to enhance an electrical signal of the first bus and an electrical signal of the second bus. The forward bias module is configured to forward bias the voltage of the first bus and the voltage of the second bus.
Non-volatile memory using a reduced number of interconnect terminals
A first signal may be received from a memory device at a first interconnect terminal of a number of interconnect terminals via a serial communication interface that indicates the memory device includes a NAND type memory device. Whether a second signal that indicates the NAND type memory device is initialized has been received from the memory device at a second interconnect terminal of the number of interconnect terminals may be determined. An operation associated with the NAND type memory device may be performed at the second interconnect terminal and a third interconnect terminal in response to determining the second signal has been received from the memory device indicating the NAND type memory device is initialized.
METHOD FOR TRANSMITTING CONTROL INSTRUCTION, TRANSMITTING DEVICE, AND RECEIVING DEVICE
Provided are a method for transmitting a control instruction, a transmitting device and a receiving device. The method includes the follows. A first control instruction is obtained by a transmitting device. the first control instruction is encapsulated into a first protocol data stream. The first protocol data stream is superimposed, by the transmitting device through a first coupling network, on a second protocol data stream in the form of differential signal generated according to multimedia data to obtain a first signal, and the first signal is transmitted to a receiving device via a cable. The first signal is filtered by the receiving device to obtain a first protocol data stream, and the first protocol data stream is decapsulated to obtain a first signal. By adopting the disclosure, transmitting control instruction via the cable can realize controlling the target device connected to the receiving. The user experience is high.
Identifying critical thermal conditions in multiple system-on-a-chip (SoC) systems
Techniques for identifying thermal critical conditions in devices with multiple SoCs, and coordinating the resetting and rebooting of the SoCs to recover from the thermal critical conditions are described herein. A device may include a first SoC that monitors a first temperature sensor, and a second SoC that monitors a second temperature sensor, to determine whether temperatures in the device indicate thermal critical conditions. The second SoC may determine that a temperature determined using the second temperature sensor is above a threshold indicating a thermal critical condition, and may provide an indication to the first SoC that the temperature is above the threshold. The first SoC may detect the indication, and the first SoC and second SoC may each reset to allow the device to cool down. The first SoC and second SoC may then coordinate rebooting once the thermal critical condition is no longer detected in the device.
I2C standard compliant bidirectional buffer
Disclosed embodiments include a serial buffer device comprising first and second serial input/output (I/O) ports, first and second comparators, and a multiplexer having a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. There is also a transistor, a third comparator having first and second inputs and an output, wherein the first input is coupled to the second serial I/O port, the second input is coupled to a third reference voltage source, and the output is coupled to the control terminal of the multiplexer. Additionally, the embodiment includes an impedance controlled driver circuit having an input and an output, wherein the input is coupled to the output of the third comparator and the output is coupled to the first serial I/O port.
COMMUNICATION SYSTEMS WITH SERIAL PERIPHERAL INTERFACE FUNCTIONALITY
Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.
DATA CONVERSION DEVICE AND DATA CONVERSION SYSTEM
A data conversion device is used between a host terminal and an equipment terminal. The equipment terminal is equipped with an RS-232 connection port. The host terminal includes a USB docking port. The data conversion device includes an RS-232 docking port, a micro controller and a USB connection port. The RS-232 connection port is connected with the RS-232 docking port. The RS-232 docking port receives each one-byte data from a RS-232 protocol data packet of the RS-232 connection port in sequence. The micro controller is connected with the RS-232 docking port, after receiving the RS-232 protocol data packet of the RS-232 docking port and setting the RS-232 protocol data packet of the RS-232 docking port into a USB-HID protocol data packet.