A bridge device includes: a first interface configured to receive a first set of commands from an application running on a host computer; one or more command processors, each of the one or more command processors being configured to translate the first set of commands and generate a second set of commands based on the first set of commands; a second interface configured to provide the second set of commands to a data storage device; and a computing processor configured to issue an internal command to fetch data from the data storage device and write data to the data storage device in a background mode in an agnostic manner to the host computer while running the application.

Virtual machines in a computer system cluster, or cloud environment, require access to their assigned storage resources connected to the virtual machines via storage area networks (SAN). Such virtual machines may be independent from associated physical servers in the computer system cluster on which they are deployed. These virtual machines may dynamically migrate among assigned physical servers while maintaining access to their connected storage resources both from the source physical server and the target physical server during the migration.

Systems and methods for managing a production server using a storage array. In an illustrative, non-limiting embodiment, a storage array may include a memory coupled to a processor, the memory having program instructions configured to cause and/or enable the storage array to: receive hardware information from a multipath input/output (MPIO) module of each of a plurality of production servers in communication with the storage array; provide the hardware information to a management server in communication with the storage array; receive a command from the management server targeting a selected production server; and transmit the command to a selected MPIO module of the selected production server.

Hardware error detection on a high-speed serial (HSS) connection including tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data: inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample; incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample; clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and incrementing, by the hardware state machine, a sample count in a sample count register.

Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit, called a KTI (Keizer Technology Interface) Flit, is implemented in a coherent multi-layer protocol supporting coherent memory transactions. The KTI Flit has a basic format that supports use of configurable fields to implement KTI Flits with specific formats that may be used for corresponding transactions. In one aspect, the KTI Flit may be formatted as multiple slots used to support transfer of multiple respective pieces of transaction data in a single Flit. The KTI Flit can also be configured to support various types of transactions and multiple KTI Flits may be combined into packets to support transfer of data such as cache line transfers.

The present disclosure relates to an integrator for a storage device, a corresponding storage device and a method of manufacturing the same. The integrator comprises a base board comprising a first interface and a second interface; a connector coupled to the first interface of the base board, the connector being connectable with at least one server in the storage device; an input/output (I/O) part coupled to the second interface of the base board and connectable with an I/O device; and a switcher arranged on the base board and adapted to exchange data between the first interface and the second interface to support data transmission of the I/O device or other servers with the server via the integrator.

Systems, methods, and apparatus are described that enable single-cycle pre-emption on a serial bus. An apparatus is coupled to a serial bus through a bus interface and includes a controller configured to provide a clock signal on the first line of the serial bus, transmit data on a second line of the serial bus in accordance with timing provided by the clock signal, cause the line driver to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line, detect a first pulse on the clock signal while the line driver is in the high impedance state, cause the line driver to exit the high impedance state prior to transmitting a second edge in the clock signal, and initiate bus arbitration after detecting the first pulse. The first edge and the second edge may transition in opposite directions.

A system and method to allocate serial interconnection lanes on a die to multiple communication protocols is disclosed. The die has at least one processing core. The die incudes a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data, and a data interface coupled to the core. The die includes a second communication subsystem including a controller, a PCS for interchanging data, and a data interface coupled to the core. A mode input selects at least one of the first or second communication protocol. A data router has an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem. The data router has an output coupled to the set of serial interconnection lanes, and a selection input coupled to the mode input to allocate some of the lanes for the selected protocol.

A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.

Executing connections from a data processing system to a storage controller using ports specified in a TPG report. The storage controller receives a RTPG SCSI request from the data processing system via a FC fabric. The storage controller determines whether NPIV is enabled on the storage controller and, if so, the storage controller modifies the TPG report to include one or more dedicated N-Ports and one or more multi-purpose N-Ports, where AAS bits of a dedicated N-Port descriptor associated with the dedicated N-Ports are set as Active/optimized. The storage controller sends the modified TPG report to the data processing system. The storage controller then processes an access request received from the data processing system where the access request is received on one of the one or more dedicated N-Ports and the one or more multi-purpose N-Ports according to the TPG report and a device type of the data processing system.