A subscriber station for a serial bus system. The subscriber station has a communication control device for controlling a communication of the subscriber station with at least one other subscriber station of the bus system and for generating a transmit signal according to a frame; a receiving device configured to serially receive at least one signal from the bus; and a tamper check module for checking whether at least one predetermined field of a frame received from the at least one signal received from the bus has at least one pulse having a second bit value, which is inverse to the predetermined first bit value, in a received bit which has a predetermined first bit value and a predetermined duration.

Disclosed herein is a system, including a microcontroller unit (MCU) and a plurality of reconfigurable devices connected to the MCU in a daisy chain arrangement via a Serial Peripheral Interface (SPI) protocol. Each reconfigurable device includes control circuitry configured for operating in both a Digital Input/Output (DIO) mode and an IO-Link mode, a digital logic for switching the DIO control circuitry between the DIO mode and the IO-Link mode, output drivers connected between outputs of the control circuitry and respective output pins of a plurality of pin sets, input filters connected between inputs of the control circuitry and respective inputs pins of the plurality of pin sets, and an SPI interface for communication with the MCU and other reconfigurable devices in the daisy chain, with the digital control facilitating communication between the SPI interface and the control circuitry.

A method for a listening network node is described herein. In accordance with one embodiment, the method includes receiving data from a serial bus interface, wherein the data includes (at least) a first header of a first data frame. The method further includes detecting completion of the reception of the first header and detecting whether the data received subsequent to the first header includes a recessive bit and storing information that indicates whether or not a recessive bit has been detected. Furthermore, the method includes detecting a stop bit in the data received subsequent to the first header and, when the detection of the stop bit fails, detecting a break delimiter that indicates the end of a break field of a second header, signaling a frame error if the stored information indicates that a recessive bit has been received, and signaling a missing response if the stored information indicates that a recessive bit has not been received.

Methods and devices are provided in which a hardware control manager of an electronic device configures a die-to-die (D2D) constraint for a topology. The hardware control manager manages a D2D interface. The hardware control manager performs D2D synchronization based on the D2D constraint. The hardware control manager configures an inter-accelerator link constraint for the topology. The hardware control manager manages a high-speed inter-accelerator link. The hardware control manager performs high-speed inter-accelerator link synchronization based on the inter-accelerator link constraint. The hardware control manager monitors the D2D interface and the high-speed inter-accelerator link based on the topology.

A first slave device and a second slave device to which different slave identifiers are added are connected to a serial bus. The second slave device includes a second storage unit including multiple registers and a second serial interface unit that receives a command in which the slave identifier of the second slave device is set via the serial bus and that sets a result of a process corresponding to the received command in at least one register in the second storage unit.

Various aspects of the present disclosure generally relate to memory device high-speed interface training. In some aspects, a memory device may perform an initial training operation for a high-speed interface of the memory device. The memory device may detect, after a completion of the initial training operation for the high-speed interface, whether an aging counter associated with the high-speed interface has expired. The memory device may initiate one or more re-training operations for the high-speed interface based at least in part on whether the aging counter has expired. In some other aspects, the memory device may detect that the memory device is in an idle state. The memory device may perform a micro-training operation for a high-speed interface of the memory device in accordance with the memory device being in the idle state. Numerous other aspects are described.

Methods for chiplet communication and accompanying chiplets, integrated circuits, design structures are disclosed herein. According to an embodiment, a method of chiplet communication includes receiving, at a chiplet, a command via a serial peripheral communication interface. The method further includes parsing, by the chiplet in an uninitialized state, the command into a packet associated with an operation performable by the chiplet and performing, by the chiplet in the uninitialized state, the operation based on the command parsed. Chiplets and chiplet communication as described may be useful for configuring or initializing out of reset chiplets using a secondary or peripheral serial interface, for example, for extra short range link bring-up or peripheral component interface express initialization.

An information processing apparatus includes a plurality of SPI memory ICs connected to a control unit by an SPI (Serial Peripheral Interface), and a printed board mounted with the SPI memory ICs. The printed board includes an expansion pad pattern which is a soldering pad pattern at a terminal of at least one of the SPI memory ICs and is arranged to extend around the IC so that a writing jig is connectable to the terminal, a through hole for positioning when connecting the writing jig to the terminal, and a conductor part connected to a chip select terminal of each of the SPI memory ICs so that one of the SPI memory ICs is selectable from the writing jig.

A communication module includes: an amplification control device connected to a main device to receive, from the main device, a main signal including a command signal, an address signal that identifies an address of at least one register included in an antenna switch and a band select switch, and a write data signal to be recorded in a register corresponding to the address and interpret the command signal; and the antenna switch and the band select switch connected to the amplification control device via a first signal line where a clock signal is transmitted and a second signal line where a data signal is transmitted.