Techniques for concurrent transmission of audio and ultrasound are described. In an example, a computing device generates, in a digital domain, mixed audio data from multiple sets of audio data, each set corresponding to a different audio channel. The computing device also generates, in the digital domain, ultrasound data, and generates serial data by providing the mixed audio data and the ultrasound data as different inputs to an I2S mixing module. In an analog domain, the computing device generates an output signal based at least in part on the serial data, and sends the output signal to a speaker.

A data transmission method according to an I2C protocol and a transmission apparatus includes: a first transmission chip obtains I2C data from a first device, wherein the I2C data is data sent by the first device to a second device. The first transmission chip sends first feedback information to the first device, wherein the first feedback information is used to indicate whether the I2C data is successfully received. The first transmission chip forwards the I2C data to a second transmission chip corresponding to the second device. The first transmission chip receives second feedback information from the second transmission chip, and the second feedback information is used to indicate whether the I2C data is successfully received. The first transmission chip stores the second feedback information in a first storage space that is storage space of the first transmission chip.

Deselect times can be specified for transactions that are to utilize a communication bus shared by multiple devices. A host can communicate with a multiplexer to select a channel for communication on that bus. If this host communicates with the multiplexer over the bus as well, the host can be prevented from instructing the multiplexer to deselect a channel if the bus is hung. To provide for recovery in such situations, one or more deselect times can be specified for one or more channels of a bus. If a transaction for a device on one of these channels is ongoing when the deselect time is reached, the multiplexer can automatically deselect that channel in order to enable other devices to communicate over other channels on that bus. In some embodiments, a riskiness of a transaction or device can be determined for purposes of applying or determining a relevant deselect time.

Provided are a method and apparatus for multi-bus device fused access. The method includes: receiving, by a bus, an instruction for accessing a fused node of a device, which instruction containing a matching word, an initial address, and an offset; performing matching according to the matching word and activating a fused drive; acquiring, by the fused drive, the initial address and the offset from the instruction on the bus respectively; computing an address of a first bus of the device according to the initial address, and computing an address of a second bus of the device according to the initial address and the offset; and accessing the device according to the address of the first bus so as to acquire first information, and accessing the device according to the address of the second bus so as to acquire second information.

A master-slave interchangeable power supply device, a power supply method, a host with the master-slave interchangeable power supply device, and a computer-readable storage medium for use in execution of the power supply method are provided. Upon receipt of a start command, a power control module and a power supply unit of the power supply device operate in a master mode and a slave mode respectively, and then the power supply device provides a working power to a master device to effect related configuration of the power supply device, so as to allow the power control module to switch to the slave mode and allow the working power to be provided to the master device. Therefore, given compliance with a specification of a communication bus, the power control module and the power supply unit, which function as peripheral devices, can perform a communicative function.

A transmission device according to an aspect of the present disclosure communicates with a reception device via a control data bus. The transmission device includes a generation unit that generates an interrupt request, and a transmission section that transmits data to the reception device via the control data bus. The interrupt request includes at least an identification bit to identify a type of transmission data, an information bit for the transmission data, and the transmission data.

An inter integrated circuit (I.sup.2C)-based communication method incudes when an I.sup.2C signal is encapsulated into a data packet for transparent transmission, an I.sup.2C status is indicated by a first field in a packet header of the data packet. The data packet may have no load part, or the data packet has a load part but the load part is used to carry a slave address, a read/write flag, or I.sup.2C data. Because the I.sup.2C status is indicated in the packet header of the data packet, the I.sup.2C status may be encapsulated in a same data packet together with the slave address, the read/write flag, or the I.sup.2C data. In other words, the I.sup.2C status may not need to occupy one data packet separately.

An I2C wake-up circuit, method and electronic device are disclosed. The I2C wake-up circuit includes: a clock wake-up circuit, configured to send a clock wake-up signal to a clock circuit in response to detecting a start signal on a serial clock line SCL and a serial data line SDA; and a signal hold circuit, configured to hold the serial data line SDA in a state of not transmitting address information until a clock signal sent by the clock circuit that is wake-up is received. The present I2C wake-up solution can realize normal data reception through a simple hardware circuit without a specific address wake-up and maximize power saving by turning on the clock when there is access and turning off the clock when the access ends.

According to one embodiment, a path obfuscation system includes first and second hardware devices, and first and second interfaces configured to provide communication between the first and second hardware devices using a security protocol and data model (SPDM) protocol. The first hardware device comprises computer-executable instructions to receive a message to be transmitted to the second hardware device, segment the message into multiple groups of packets, and randomly select either the first or second interface to transmit each group of packet to the second hardware device.

An IC is provided. The IC includes an input pin, a controller, a timer, a first memory, a processor, at least one output pin, an output module coupled to the output pin, and a direct memory access (DMA) device coupled between the output module and the first memory. The controller is configured to provide a first control signal in response to a command from the input pin. The timer is configured to periodically provide a trigger signal according to the first control signal. The processor is configured to store first data in the first memory. The DMA device is configured to obtain the first data from the first memory in response to the trigger signal, and transmit the first data to the output module. The output module is configured to provide the first data to the output pin according to a transmission rate.