Battery management systems and methods for using the same to obtain battery shock and/or rollover data. An exemplary battery management system of the present disclosure comprises an accelerometer configured to obtain acceleration data, a microcontroller operably connected to the accelerometer and configured to receive the acceleration data from the accelerometer, and a data storage medium in communication with the microcontroller, the data storage medium configured to store the acceleration data therein, wherein when the battery management system is in communication with a battery, the accelerometer can obtain the acceleration data relating to the battery, and the microcontroller can operate to disconnect the battery from a load connected thereto should the acceleration data meet or exceed a threshold limit.

One embodiment of the present invention discloses a two-phase configuration process (“TCP”) to configure a field-programmable gate array (“FPGA”) to include a configurable microcontroller unit (“CMU”) during a phase I configuration and configuring the CMU during a phase II configuration. TCP, in one aspect, is able to receive first configuration data from a first external storage location via a communication bus. After storing the first configuration data in a first configuration memory for configuring FPGA to contain a CMU for the phase I configuration, second configuration data with MCU attributes is obtained from a second external storage location via the communication bus. The second configuration data is subsequently stored in a second configuration memory for programming the CMU for the phase II configuration.

An I2C bus communication control method, device and system, and a readable storage medium. The method comprises: receiving configuration information of an I2C bus sent by an upper-layer application; analyzing the configuration information to obtain a plurality of polling parameters; writing the plurality of polling parameters into a polling table; and controlling the I2C bus, and executing a corresponding read-write operation according to the polling table. In the method, the read-write operation executed on the I2C bus is performed according to the polling table, thus an accurate communication condition of the I2C bus can be directly obtained on the basis of the polling table without accessing a bus state in a polling manner; congestion risks can be reduced, and the access efficiency of a single main device can also be achieved when a plurality of main devices exist.

Embodiments of systems and methods for high-availability (HA) management networks for High Performance Computing (HPC) platforms are described. In some embodiments, an HPC platform may include a first Baseboard Management Controller (BMC) having a first network port; and a hardware accelerator comprising a second BMC having a second network port, where at least one of: (a) the first BMC is configured to share the first network port with the second BMC in response to a determination that the second network port has failed or has insufficient bandwidth, or (b) the second BMC is configured to share the second network port with the first BMC in response to a determination that the first network port has failed or has insufficient bandwidth.

In an example, a method comprises, by logic circuitry associated with a replaceable print apparatus component, responding to a first validation request sent via an I2C bus to a first address associated with the logic circuitry with a first validation response; and responding to a second validation request sent via the I2C bus to a second address associated with the logic circuitry with a second validation response.

The present application relates to the field of display technology, and discloses a display module test platform, including a core processor. The core processor is capable of supporting installation of a terminal operating system. A display output terminal of the core processor is connected to a display module to be tested. The display module to be tested includes a touch structure. The touch structure and the core processor communicate with each other via an Inter-Integrated Circuit (I2C) bus.

Embodiments of systems and methods for high-speed Out-of-Band (OOB) management links for inter-Baseboard Management Controller (BMC) communications in High Performance Computing (HPC) platforms are described. In some embodiments, an HPC platform may include: a system BMC; and an accelerator tray comprising: (a) one or more managed subsystems, (b) a tray BMC coupled to the one or more managed subsystems, and (c) a Field-Programmable Gate Array (FPGA) coupled to the tray BMC and to the system BMC.

An information handling system includes a memory and a baseboard management controller. The memory stores one or more device update packages, and each of the first device update packages includes an inter-integrated circuit payload. The baseboard management controller receives a first device update package, and stores the first device update package in the memory. In response to the first device update package being stored in the memory, the baseboard management controller launches a handler. The baseboard management controller retrieves a bus number and an address for a target device identified in the first device update package. The baseboard management controller parses data in a body of the inter-integrated circuit payload of the first device update package, and executes inter-integrated circuit commands in the body to provide a firmware image update to the target device.

A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

A hybrid mode system containing an external device and a field-programmable gate array (“FPGA”) capable of providing configuration data to FPGA via a hybrid communication channel is disclosed. The system is able to identify a first communication protocol in accordance with at least a portion of address bits presented on a serial data line (“SDA”) wherein SDA is used as a connection between FPGA and the external device. The clock signals for receiving data are adjusted to a first clock frequency in accordance with the first communication protocol and clock cycles presented on a serial clock line (“SCL”). SCL is used to connection between FPGA and the external device. After transmitting the configuration data, a portion of FPGA is programmed to perform user-defined logic functions in response to the configuration data.