A mechanism is provided in a data processing system comprising at least one processor and at least one memory, the at least one memory comprising instructions that are executed by the at least one processor and configure the at least one processor to implement a device context device driver for forced detaching of an application from mapped devices. The device context device driver receives a command to detach an application, wherein the command specifies a process descriptor associated with the application. The device context device driver identifies a plurality of matching device context entries in a list of open device contexts maintained by the device context device driver that match the process descriptor. The device context device driver marks the plurality of matching device context entries as detached. The device context device driver invalidates mapped memory areas associated with the plurality of matching device context entries. The device context device driver shuts down all device contexts associated with the plurality of matching device context entries.

A switch fabric is disclosed that includes a serial communications interface and a. parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

Technologies for performing a secure firmware update include a compute device that includes a memory device to store firmware update payload, one or more devices that have direct memory access (DMA) to the memory, a DMA remap module, and a firmware update module. The DMA remap module is to create a memory isolation domain for each of the one or more devices. Each memory isolation domain comprises a physical address space in the memory that is mutually exclusive to the physical address spaces of the other memory isolation domains. The firmware update module is to (i) analyze the firmware update payload to identify one or more of the devices associated with the firmware update payload and (ii) move the firmware update payload to the memory isolation domains of each associated device to enable secure transmission of the firmware update payload to the associated devices.

An integrated circuit (IC) implements an industry standard-defined peripheral interconnect to connect to another integrated circuit or component in a system. The industry standard specification includes a software interface that is well-defined and implemented by various software in the system, and thus is desirable to retain. However, the physical interconnect in the systems employing the integrated circuit may be short, and thus the elaborate physical layer definition may consume more integrated circuit area and power than is otherwise desirable in the IC. The IC may implement a simpler and more power-efficient physical layer, reducing both power consumption and semiconductor substrate area consumption, in some embodiments.

A method for providing a virtual optical disk drive (ODD) is provided. The method can comprise: simulating a PCI IDE controller through PCI configuration space IO trap and simulating the ODD through IDE device IO trap.

A central processing unit executes a graphics accelerated operation during a pre-boot basic input/output system (BIOS). The central processing unit initializes multiple protocol scheduler circuitry during an early phase of the pre-boot BIOS. The multiple protocol scheduler circuitry initializes host memory pages, and creates one or more bit block transfer tasklets during the pre-boot BIOS. A graphics processing core executes one of the bit block transfer tasklets, and renders a graphical user interface element for display during the pre-boot BIOS.

An information handling system may reset components logged in a memory of the information handling system. For example, an information handling system may determine components logged in an information handling system memory and may perform a bulk reset of the logged components.

A firmware enumerates the buses of root bridges in the computing system. If an OOR condition occurs during enumeration of the buses, the firmware determines the number of required buses for each root bridge causing an OOR condition. The number of required buses for bridge devices connected to each root bridge causing an OOR condition can be identified using the same set of bus numbers. Once the firmware has determined the number of buses required by each root bridge, including those not causing an OOR condition, the firmware reallocates the number of available buses between the root bridges such that each root bridge is allocated a number of the available buses greater than or equal to the number of required buses. The firmware stores data identifying the allocation and restarts the computing device. Upon rebooting, the computing system utilizes the new allocation of bus numbers to eliminate the OOR condition.

An information handling system may include a processor, a network interface, and a basic input/output system (BIOS) configured to execute a pre-boot environment. The information handling system may be configured to: during execution of the pre-boot environment, establish a pre-boot network connection to a remote information handling system via the network interface; receive operating system data from the remote information handling system; create a pseudo-device at a specified address of the information handling system; perform direct memory access (DMA) remapping between the pseudo-device and an address range of memory of the information handling system to create a ram disk; and based on the operating system data received from the remote information handling system, initialize an operating system on the ram disk via the specified address of the pseudo-device.

A CPU module (100) includes a first bus complying with a first communication protocol, and a second bus complying with a second communication protocol different from the first communication protocol. A conversion setting storage (110) included in the CPU module (100) stores information indicating association between a general instruction complying with the first communication protocol and a dedicated instruction complying with the second communication protocol. A protocol converter (160) included in the CPU module (100) acquires, when the general instruction is output by instruction output means to a device connected via the second bus, the dedicated instruction associated with the general instruction from the conversion setting storage (110) and provides the acquired dedicated instruction to the device via the second bus.