A system timer bus used by the processor elements in an ARM-based system on a chip (SoC) is driven using a Precision Time Measurement (PTM) value. This allows the processor elements to be synchronized to the PCIe ports that use PTM. When two SoCs are connected using PCIe links, this example allows the processor elements in both SoCs to be synchronized. As the processor elements are synchronized, associated tasks on the two SoCs are synchronized, so that overall operations are synchronized.

Bus enumeration of a switch fabric bus may be performed without assigning bus numbers to unused switch ports and/or corresponding slots to which the unused switch ports are routed. Accordingly, switches coupled to a switch fabric bus in a chassis may link-train with corresponding slots in the chassis in an attempt to establish active connections with devices coupled to the slots. Unused switch fabric bus lanes running from the switches to unused slots may be identified, and the unused switch ports corresponding to the unused switch fabric bus lanes may be disabled. During a subsequent bus enumeration procedure for the switch fabric bus, bus numbers may be allocated to the identified used switch ports (or corresponding used slots) but not to the identified unused switch ports (or corresponding unused slots). The link training, used/unused switch port identification, and bus enumeration may all be performed each time the chassis is reset.

Various embodiments provide methods for Internet Protocol (IP) packet handling. Various embodiments may enable downlink (DL) data prioritization of IP packets for time-sensitive applications, for example by using differentiated services code point (DSCP) indications or type-of-service (TOS) indications in headers of the IP packets to distinguish prioritized IP packets from non-prioritized IP packets. In various embodiments, IP packets that are prioritized IP packets may be sent to another processor of a wireless device using a prioritized traffic handling configuration that has a lower latency than a default traffic handling configuration used for sending non-prioritized IP packets. Various embodiments may further enable uplink (UL) data prioritization of IP packets.

A configurable multi-function Peripheral Component Interchange Express (PCIe) endpoint controller, integrated in a system-on-chip (SoC), that exposes multiple functions of multiple processing subsystems (e.g., peripherals) to a host. The SoC may include a centralized transaction tunneling unit and a multi-function interrupt manager. The processing subsystems output data to the host via the centralized transaction tunneling unit, which translates addresses provided by the host to a local address of the SoC. Therefore, the centralized transaction tunneling unit enables those processing subsystems to consume addresses provided by the host without the need for software intervention and software-based translation. The SoC may also provide isolation between each function provided by the processing systems. The multi-function interrupt manager enables the endpoint controller to propagate interrupt messages received from the processing subsystems to the host.

A PCIe-based communications system includes a first processor and a plurality of switches, the plurality of switches include a first switch and a second switch, a first link exists between the first processor and the first switch, a second link exists between the first switch and the second switch, and a first standby link is configured between the first processor and the second switch. If the first link and the second link are not faulty, communicating, by the first processor, with the second switch through the first link and the second link; or if the first link or the second link is faulty, activating the first standby link, and communicating, by the first processor, with the second switch through the activated first standby link. Thereby stability of the communications system can be improved.

Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

Systems and corresponding methods employ an object-oriented (OO) memory (OOM) to effect inter-hardware-client (IHC) communication among a plurality of hardware clients included in same. A system comprises a centralized OOM and the plurality of hardware clients communicate, directly, to the centralized OOM device via OO message transactions. The centralized OOM device effects IHC communication among the plurality of hardware clients based on the OO message transactions. Another system comprises a plurality of OO memories (OOMs) capable of inter-object-oriented-memory-device communication. A hardware client communicates, directly, to a respective OOM device via OO message transactions. The inter-object-oriented-memory-device communication effects IHC communication among the plurality of hardware clients based on the OO message transactions.

A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root I/O virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.

A network interface device has data path circuitry configured to cause data to be moved into and/or out of the network interface device. The data path circuitry comprises: first circuitry for providing one or more data processing operations; and interface circuitry supporting channels. The channels comprises command channels receiving command information from a plurality of data path circuitry user instances, event channels providing respective command completion information to the plurality of data path user instances; and data channels providing the associated data.

Multiple independent endpoint devices can be emulated using a single system on chip (SoC) device. Such a SoC can have multiple cores that can emulate ports according to a specified protocol, such as the peripheral component interconnect express (PCIe) protocol useful for data communications. An emulation agent can manage various aspects of these emulated endpoint devices in software, including serving interrupts for relevant emulated devices according to a determined priority scheme. Interrupts can be registered for each device, and data structures allocated dynamically for a determined number and type(s) of PCIe endpoint devices to be emulated. Each PCIe core on the SoC can function as a separate PCIe endpoint device endpoint for communicating with one or more hosts or other such devices.