An information processing system includes a host and a storage device that transmits a first pulse signal to the host and receives a second pulse signal from the host through a transmission line. The storage device has a first register to store a value of a first parameter and correction circuit to adjust a first duty ratio of the first pulse signal according to the value of the first parameter. The host includes a first calibration processor that measures a plurality of the first duty ratios as output from the storage device for different values of the first parameter to derive a first optimum value based on the measured first duty ratios and transmit the derived first optimum value to the storage device as the value of the first parameter to be stored in the first register.

A computer system including a frame, components and a pair of stacked controllers. The system also includes a plurality of midplanes positioned between the components and the controllers where each midplane includes a component edge and a controller edge, a first midplane connector coupled to the component edge and a second midplane connector coupled to the controller edge, where the first midplane connector is coupled to one of the component connectors and the second midplane connector is coupled to one of the controller connectors so that the midplanes are vertically oriented in parallel so as to define spaces therebetween. In one embodiment, the computer system is a data storage system, the components are storage drives and the controllers are storage controllers.

A device connectable between a host computer and a computer peripheral over a standard bus interface is disclosed, used to improve security, and to detect and prevent malware operation. Messages passing between the host computer and the computer peripherals are intercepted and analyzed based on pre-configured criteria, and legitimate messages transparently pass through the device, while suspected messages are blocked. The device communicates with the host computer and the computer peripheral using proprietary or industry standard protocol or bus, which may be based on a point-to-point serial communication such as USB or SATA. The messages may be stored in the device for future analysis, and may be blocked based on current or past analysis of the messages. The device may serve as a VPN client and securely communicate with a VPN server using the host Internet connection.

Embodiments presented herein provide for hot swappable connections to various storage devices. In one embodiment, a storage controller includes an interface operable to connect to at least one of a storage device and a midplane connected to a plurality of Non Volatile Memory Express (NVMe) storage devices. The storage controller also includes a processor operable to detect when the interface is connected to the mid-plane, to determine that the NVMe storage devices each have a x4 NVMe connection, and to communicate sideband signaling, including a reference clock, to the NVMe storage devices through the midplane via Inter-Integrated Circuit (I2C) upon determining that the NVMe storage devices each have a x4 NVMe connection.

A system includes a fabric switch including a motherboard, a baseboard management controller (BMC), a network switch configured to transport network signals, and a PCIe switch configured to transport PCIe signals; a midplane; and a plurality of device ports. Each of the plurality of device ports is configured to connect a storage device to the motherboard of the fabric switch over the midplane and carry the network signals and the PCIe signals over the midplane. The storage device is configurable in multiple modes based a protocol established over a fabric connection between the system and the storage device.

According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to execute a patrol process, in response to a first command set from a host device. In the patrol process, the memory controller is configured to read first data from the nonvolatile memory, and not to output the first data to the host device.

In computing scenarios involving multiple computational units, an enclosure (e.g., a rack or server cabinet) may store the units and provide resources such as shared power and network connectivity. Additionally, the components of the units may communicate through a Serial Attached SCSI (SAS) bus, but many such enclosures provide little or no integration with the SAS buses, thus entailing extensive SCSI cabling. Presented herein are architectures for enclosures presenting a set of slots for trays storing respective computing blades, where such trays include SAS connectors that connect directly (i.e., without cabling) with connectors on a midplane that interconnects the blades into a SAS bus featuring at least one integrated SAS expander. Additional architectural variations involve providing SAS expander on one or both of the midplane and the blades; grouping blades into subsets having distinct SAS buses; and interconnecting the SAS buses and expanders of multiple midplanes in the enclosure.

Aspects of the present disclosure are directed to performing varying frequency memory sub-system background scans using either or both a timer and an I/O event limit. This can be accomplished by identifying a background scan trigger event from one of multiple possible types of background scan trigger events, such as a timer expiration or reaching an event count limit. In response to the background scan trigger event, a background scan can be initiated on a memory portion. The background scan can produce results, such as CDF-based data. When a metric based on the results exceeds a background scan limit, a refresh relocation can be performed and logged. A metric can be generated based on the CDF-based data, obtained error recovery depth data, or refresh relocation event data. When the metric is above or below corresponding background scan thresholds, a background scan frequency can be adjusted.

A storage array and systems for configuring a storage array are provided. In one example, the storage array includes a motherboard. The motherboard includes a first compute module and an input/output (I/O) mid-plane that is routed to the first compute module. The I/O mid-plane has a plurality of peripheral component interconnect express (PCIe) lanes coupled to the first compute module. A bridge module interconnect is routed to the I/O mid-plane via one or more of the plurality of PCIe lanes of the I/O mid-plane. The bridge module interconnect provides bridge connections to receive to two or more types of protocol bridge modules. A storage mid-plane provides integrated routing between each of a plurality of drive connectors and each of the bridge connections of the two or more types of protocol bridge modules of the bridge module interconnect. In some configurations, the I/O mid-plane is eliminated and that functionality is integrated into a combination of boards referred to as upper and lower storage docking modules, while maintaining the storage mid-plane.

An optical module link negotiation information obtaining method, a device, and a system are provided to include: obtain first information of an optical module readable partition; when the partition indicated by the first information is different from a partition that stores link negotiation information in the optical module, and a recorded quantity of optical module link negotiation information obtaining times does not reach a preset threshold, modify the first information of the optical module readable partition into information indicating the partition that stores the link negotiation information to make the partition that stores the link negotiation information as an updated optical module readable partition; and re-obtain second information of the updated optical module readable partition, and when the updated partition indicated by the second information is the same as the partition that stores the link negotiation information in the optical module, obtain optical module link negotiation information.