The present disclosure generally relates to reducing time for interface transmitter training based upon an assumed identify of the training partner. It is unlikely for a drive PHY to link up with multiple PHYs per power cycle. Therefore, it is a fair assumption that when there is no power loss, the drive PHY is connected to the same host device. The drive can therefore change its behavior based on the assumed identity of the host from previously exchanged identify frames, if the previously used training algorithm was sufficient for interface transmitter training for the particular host. The drive will go directly to the correct training algorithm without the need to do a PHY reset using a training algorithm that is tailored to the host and thus reduce interface transmitter training time.

A data storage system including a frame, storage drives and a pair of stacked storage controllers. The system also includes a plurality of midplanes each having a PCB with opposing side surfaces, a front edge, a rear edge and a plurality of electrical traces. Each midplane further includes a first midplane connector coupled to the front edge, a second midplane connector coupled to the rear edge and a third midplane connector coupled to the rear edge, where the first connector is coupled to drive connectors and some of the electrical traces, the second connector is coupled to a controller connector and some of the electrical traces and the third connector is coupled to another one of the controller connectors and some of the electrical traces so that the midplanes are vertically oriented in parallel to define spaces therebetween relative to a front to rear direction of the frame.

An information processing system includes a host and a storage device that transmits a first pulse signal to the host and receives a second pulse signal from the host through a transmission line. The storage device has a first register to store a value of a first parameter and correction circuit to adjust a first duty ratio of the first pulse signal according to the value of the first parameter. The host includes a first calibration processor that measures a plurality of the first duty ratios as output from the storage device for different values of the first parameter to derive a first optimum value based on the measured first duty ratios and transmit the derived first optimum value to the storage device as the value of the first parameter to be stored in the first register.

An electronic device configured to communicate with a host includes: a detecting logic configured to receive an initial command signal and a first completion signal according to the initial command signal after a connection of the host to the electronic device is established, and transmit a detection signal based on a signal transmission policy of the host that has been detected based on the initial command signal and the first completion signal; and a transmitting logic configured to transmit a second completion signal to the host based on the detection signal, wherein the signal transmission policy is different depending on whether the first completion signal is received in response to the second completion signal.

According to one embodiment, an electronic communication device includes a controller that changes an upper limit value capable of correcting an error of bit data in which an error occurs in packet data transferred by serial communication.

According to one embodiment, an electronic device includes an interface configured to carry out communication according to a predetermined protocol, and a control section configured to add a response frame to a response to a command to be received through the interface, and transmit the response to which the response frame is added through the interface. The control section includes a setting section configured to set an arbitrarily settable field included in the response frame to a plurality of sections.

According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to execute a patrol process, in response to a first command set from a host device. In the patrol process, the memory controller is configured to read first data from the nonvolatile memory, and not to output the first data to the host device.

The present disclosure generally relates to reducing time for interface transmitter training based upon an assumed identify of the training partner. It is unlikely for a drive PHY to link up with multiple PHYs per power cycle. Therefore, it is a fair assumption that when there is no power loss, the drive PHY is connected to the same host device. The drive can therefore change its behavior based on the assumed identity of the host from previously exchanged identify frames, if the previously used training algorithm was sufficient for interface transmitter training for the particular host. The drive will go directly to the correct training algorithm without the need to do a PHY reset using a training algorithm that is tailored to the host and thus reduce interface transmitter training time.

Provided is a module mounted in a server to share a block-level storage and resources. The module includes: a HBA card unit for connection to an external server; an internal disk unit providing a storage space inside a server; a setting unit allocating the storage space of the internal disk unit; a target driver unit implementing a SCSI protocol, communicating with the external server and setting volumes to a storage mode or a server mode; and a target core unit routing data of the internal disk unit and the target driver unit depending on the storage mode or the server mode. The storage mode allows the volumes to be used as a storage of the external server. The server mode allows the volumes to be used as a storage inside the server. The target driver unit can switch the volumes from the server mode to the storage mode.

A storage drive adapter may comprise an adapter board, which may include a first and second carrier module interface to removably engage with a first and a second storage drive carrier module, respectively. The adapter board may further include a dual ported storage drive connector to engage with a complementary storage drive bay interface. The dual ported storage drive connector may include a first port to provide a first signal path from the complementary storage drive bay interface to the first carrier module interface. Similarly, the dual ported storage drive connector may also include a second port to provide a second signal path from the complementary storage drive bay interface to the second carrier module interface.