In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

A device connectable between a host computer and a computer peripheral over a standard bus interface is disclosed, used to improve security, and to detect and prevent malware operation. Messages passing between the host computer and the computer peripherals are intercepted and analyzed based on pre-configured criteria, and legitimate messages transparently pass through the device, while suspected messages are blocked. The device communicates with the host computer and the computer peripheral using proprietary or industry standard protocol or bus, which may be based on a point-to-point serial communication such as USB or SATA. The messages may be stored in the device for future analysis, and may be blocked based on current or past analysis of the messages. The device may serve as a VPN client and securely communicate with a VPN server using the host Internet connection.

A solid-state drive (SSD) includes a connector communicatively coupling the SSD to a host device, a controller coupled to the connector, and a memory device. The SSD also include a regulator configured to receive an instruction to enter a low power mode of the SSD, enter the low power mode upon receipt of the instruction, receive an indication to exit the low power mode, and exit the low power mode upon receipt of the indication.

Embodiments presented herein provide for hot swappable connections to various storage devices. In one embodiment, a storage controller includes an interface operable to connect to at least one of a storage device and a midplane connected to a plurality of Non Volatile Memory Express (NVMe) storage devices. The storage controller also includes a processor operable to detect when the interface is connected to the mid-plane, to determine that the NVMe storage devices each have a x4 NVMe connection, and to communicate sideband signaling, including a reference clock, to the NVMe storage devices through the midplane via Inter-Integrated Circuit (I2C) upon determining that the NVMe storage devices each have a x4 NVMe connection.

A payload store within a database management system includes a first set of nodes that include a first node that includes a memory, a network interface, a storage device, and a processing unit. The processing unit receives, via the network interface, a first portion of data to be stored in a plurality of storage devices of the first set of nodes, and splits the first portion into a first set of data rows that includes a plurality of subsets of data rows and a last subset of data rows. The processing unit further randomly assigns the plurality of subsets of data rows and the last subset of data rows between the first set of nodes and stores a first number of data rows in the storage device. The processing unit further sends, via the network interface, a second number of data rows to the second node for storage therein.

The present invention relates to an assembly (10) for attaching a data storage device (12) to an on-board computer including an encapsulation structure (17), and a receiving structure (18) for receiving the encapsulation structure (17) comprising a first connector complementary to a connector of the storage device and a second connector complementary to a connector of the onboard computer.

The encapsulation structure (17) and the storage device (12) mounted therein are movable relative to the receiving structure (18) between an inserted configuration in which the encapsulation structure (17) and the storage device (12) are inserted into the receiving structure (18) and the connector of the storage device (12) is connected to the first connector, and a removed configuration in which the encapsulation structure (17) and the storage device (12) are removed from the receiving structure (18).

The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a physical layer output signal according to a serializer/deserializer (SerDes) reception signal; an input/output (I/O) circuit operable to generate at least one terminal output signal according to signal variation of at least one terminal; and a processing circuit operable to make the solid state drive control device adapt to one of several interface types in accordance with the physical layer output signal and/or the at least one terminal output signal.

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller’s performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to execute a patrol process, in response to a first command set from a host device. In the patrol process, the memory controller is configured to read first data from the nonvolatile memory, and not to output the first data to the host device.

According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.