G06F2213/0038

SYSTEM FOR LINK MANAGEMENT BETWEEN MULTIPLE COMMUNICATION CHIPS

Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity. In response to determining that the other integrated circuit is authorized to execute the activity, the processor circuit sends, to the other integrated circuit over a configurable direct connection, an authorization signal authorizing the other integrated circuit to execute the activity.

INFORMATION TERMINAL, INFORMATION TERMINAL CONTROL METHOD, INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, INFORMATION PROCESSING SYSTEM, AND COMPUTER PROGRAM
20230222073 · 2023-07-13 ·

An information terminal that uploads IC chip information to a server is provided.

The information terminal includes a reading unit that reads information from a recording medium at a first timing based on first information described in setting information, and an upload unit that uploads the information to an external device at a second timing based on second information described in the setting information. the recording medium is an IC chip built in the information terminal or an IC chip accessible from the information terminal. The reading unit reads IC chip information from the IC chip, and the upload unit uploads the IC chip information to the external device.

MULTIPLE PORT EMULATION

Multiple independent endpoint devices can be emulated using a single system on chip (SoC) device. Such a SoC can have multiple cores that can emulate ports according to a specified protocol, such as the peripheral component interconnect express (PCIe) protocol useful for data communications. An emulation agent can manage various aspects of these emulated endpoint devices in software, including serving interrupts for relevant emulated devices according to a determined priority scheme. Interrupts can be registered for each device, and data structures allocated dynamically for a determined number and type(s) of PCIe endpoint devices to be emulated. Each PCIe core on the SoC can function as a separate PCIe endpoint device endpoint for communicating with one or more hosts or other such devices.

Vehicle system, vehicle and method for operating such a vehicle system

A vehicle system having: a hardware level, a first operating system, and a virtual machine integrated on the hardware level having a second operating system. A hypervisor operates the virtual machine such that the first and the second operating systems) are operated in parallel on the hardware. A first application is executed on the first operating system and a second application is executed on the second operating system. The first application has a higher safety standard than the second application. The second operating system is configured to be operated in suspend-to-RAM mode while the first operating system is switched off.

Routing network using global address map with adaptive main memory expansion for a plurality of home agents
11693805 · 2023-07-04 · ·

An adaptive memory expansion scheme is proposed, where one or more memory expansion capable Hosts or Accelerators can have their memory mapped to one or more memory expansion devices. The embodiments below describe discovery, configuration, and mapping schemes that allow independent SCM implementations and CPU-Host implementations to match their memory expansion capabilities. As a result, a memory expansion host (e.g., a memory controller in a CPU or an Accelerator) can declare multiple logical memory expansion pools, each with a unique capacity. These logical memory pools can be matched to physical memory in the SCM cards using windows in a global address map. These windows represent shared memory for the Home Agents (HAs) (e.g., the Host) and the Slave Agent (SAs) (e.g., the memory expansion device).

Collection of runtime information for debug and analysis

A system on chip (SOC) system includes functional modules, including a first and second functional module. The first and second functional module are configured to send, to an aggregation module and in a standardized message format, first and second status information associated with the first and second functional module according to a first and second set of one or more reporting rules, respectively. The aggregation module aggregates the first status information in the standardized message format and the second status information in the standardized message format and insert a timestamp to obtain a timestamped and aggregated message stream. The timestamped and aggregated message stream is stored and enables a visualization system to analyze the first functional module and the second functional module.

PLATFORM FRAMEWORK TELEMETRY

Embodiments of systems and methods for platform framework telemetry are described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: receive telemetry data at a telemetry service from at least one producer registered with a platform framework via an Application Programming Interface (API); receive a request for at least a subset of the telemetry data from a consumer registered with the platform framework via the API; and transmit the subset of the telemetry data to the consumer.

PLATFORM FRAMEWORK STANDBY OPERATION

Embodiments of systems and methods for standby operation in a platform framework are described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: identify an application registered with a platform framework via an Application Programming Interface (API); and at least one of: in response to the identification matching any entry in a whitelist, put the application in a throttled state during standby operation of the IHS; or in response to the identification not matching any entry in the whitelist, put the application in a suspended state during standby operation of the IHS.

METHOD AND SYSTEM FOR DATA TRANSACTIONS ON A COMMUNICATIONS INTERFACE

A system-on-a-chip (SoC) with one or more processors and other system components may have one or more peripheral component interconnect express (PCIe) physical connections between the processors and other system components to provide agent-to-agent communication. The agents on the communication fabric of the SoC may transmit data through the hardware PCIe interface where a transmitter device of an agent or digital logic component receives at least one data block for transmission and receives a flag corresponding to the at least one data block. The transmitter device may then send, via a PCIe physical layer, the received data blocks as a payload of a packet based on the flag, where the packet has a PCIe compliant header. The payload of the packet with the PCIe header may be entirely composed of these data blocks or flits from the agent.

Enhancing diagnostic capabilities of computing systems by combining variable patrolling API and comparison mechanism of variables

Methods and apparatus relating to enhancing diagnostic capabilities of computing systems by combining variable patrolling Application Program Interface (API) and comparison mechanism of variables are described. In one embodiment, a first processor core executes a first instance of a workload to generate a first set of safety variables. A second processor core executes a second instance of the workload to generate a second set of safety variables. A third processor core generates a signal in response to comparison of the first set of safety variables and the second set of safety variables. Other embodiments are also disclosed and claimed.