Techniques are described for reconciling events timestamped in different time domains in multi-node systems supporting low-latency hardware timestamping. First and second nodes having independent time bases are synchronized by the first node generating an event that is received effectively simultaneously at the first and second nodes, the first and second nodes recording a timestamp of receipt of the event, the first node asynchronously querying the second node for its timestamp of receipt of the event and comparing its timestamp of receipt of the event with the timestamp of receipt of the event by the second node, and the first node using a difference in the timestamps of receipt of the event by the first and second nodes to align the time bases of the first and second nodes. The nodes may include hardware timestamping functionality or use an external component (e.g., field programmable gate array) to provide the timestamping functionality.

Generally, this disclosure provides systems, devices, methods and computer readable media for virtualization-based intra-block workload isolation. The system may include a virtual machine manager (VMM) module to create a secure virtualization environment or sandbox. The system may also include a processor block to load data into a first region of the sandbox and to generate a workload package based on the data. The workload package is stored in a second region of the sandbox. The system may further include an operational block to fetch and execute instructions from the workload package.

A system for providing odd modulus memory channel interleaving may include a dynamic random access memory (DRAM) system and a system on chip (SoC). The SoC comprises a first memory controller, a second memory controller, and a symmetric memory channel interleaver. The first memory controller is electrically coupled to a first DRAM module via a first memory bus. The second memory controller is electrically coupled to a second DRAM module and a third DRAM module via a second memory bus. The symmetric memory channel interleaver is configured to uniformly distribute DRAM traffic to the first memory controller and the second memory controller. The first memory controller provides a first interleaved channel to the first DRAM module via the first memory bus. The second memory controller provides a second interleaved channel to the second DRAM module via upper address bits on the second memory bus.

A system on a chip (SoC) includes a first domain comprising a first processor configured to boot the SoC, and a first debug subsystem, a second domain comprising a second processor, the second domain configurable as either a safety domain or a general-purpose processing domain, and isolation circuitry between the first domain and the second domain. During boot-up of the SoC, the first processor provides code to the second domain which, when executed by the second processor, configures the second domain as either a safety domain or as a general-purpose processing domain.

A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.

A coherent memory fabric includes a plurality of coherent master controllers and a coherent slave controller. The plurality of coherent master controllers each include a response data buffer. The coherent slave controller is coupled to the plurality of coherent master controllers. The coherent slave controller, responsive to determining a selected coherent block read command is guaranteed to have only one data response, sends a target request globally ordered message to the selected coherent master controller and transmits responsive data. The selected coherent master controller, responsive to receiving the target request globally ordered message, blocks any coherent probes to an address associated with the selected coherent block read command until receipt of the responsive data is acknowledged by a requesting client.

Present invention disclose a hardware accelerator and a chip, and the hardware accelerator includes: an interface circuit and an accelerator core coupled to the interface circuit, where the interface circuit is configured to receive a first task request, perform decoding on the first task request to acquire identifier information, and configure, according to the identifier information, the first task request to be in an FIFO queue that matches the identifier information; a scheduling controller is configured to determine, from at least two channel groups, one or more target channel groups that have at least one to-be-processed second task request in an n.sup.th period, receive a time parameter that is fed back by the accelerator core and corresponding to the target channel group, and schedule the at least one second task request in the one or more target channel groups according to the time parameter and a weighted round robin algorithm.

There is disclosed a computing apparatus, including: a memory; a memory encryption controller to encrypt at least a region of the memory; and a network interface to communicatively couple the computing apparatus to a remote host; wherein the memory encryption controller is configured to send an encrypted packet decryptable via an encryption key directly from the memory to the remote host via the network interface, bypassing a network protocol stack.

Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals and control messages over a serial communication link. An apparatus includes a serial bus, and a controller configured to represent a series of signaling state of physical general-purpose input/output (GPIO) in a batch that comprises a sequence of virtual GPIO messages and control messages, generate a first header that includes timing information configured to control timing of execution of the batch, transmit the first header over a communication link, and transmit the batch over the communication link.

Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.