There is disclosed in one example an apparatus, including: a plurality of interconnects to communicatively couple an accelerator device to a host device; and an address translation module (ATM) to provide address mapping between host-physical address (HPA) and guest-physical address (GPA) spaces for the accelerator device, wherein the plurality of devices share a common GPA domain and wherein address mapping is to be associated with only one of the plurality of interconnects.

A method for programming and controlling of a plurality of slave devices serially connected in a daisy chain configuration using a master device includes assigning a unique slave address to each slave device in the plurality of slave devices by sending an initialization data packet from the master device serially through the plurality of slave devices; storing, in each of the plurality of slave devices, the assigned slave address; defining a data packet; and transmitting the data packet serially to one or more of the plurality of slave devices. The data packet has a target slave address, a read/write command, a start address, and optionally a register address and an increment value.

A method for programming and controlling of a plurality of slave devices serially connected in a daisy chain configuration using a master device is disclosed. The method includes broadcasting, from the master device, an initialization data packet to the plurality of slave devices to assign each slave device in the plurality of slave devices a slave address that is unique to said each slave device; storing, in each slave device, the assigned slave address, defining a data packet , wherein the data packet comprises a target slave address, a read/write command, a register address, a increment value, and a start address; and transmitting the data packet serially to one or more of the plurality of slave devices until the target address in the data packet matches the slave address stored in one of the plurality of slave devices.

An information handling system includes an identification resistor, calibration circuitry, and a system-on-a-chip (SOC). The SOC sets the calibration line to a first digital state to place the calibration circuitry in an inventory mode. While the calibration circuitry is in the inventory mode, the SOC determines an inventory amount of time to charge the capacitor to a voltage substantially equal to a threshold voltage. The SOC then sets the calibration line to a second digital state to place the calibration circuitry in a calibration mode. While the calibration circuitry is in the calibration mode, the SOC determines a calibration amount of time to charge the capacitor to the voltage substantially equal to the threshold voltage. The SOC determines a resistance of the identification resistor based on the inventory amount of time and the calibration amount of time. The SOC also determines bit strapping information corresponding to the determined resistance.

A multichip system includes a transmitter-end chip and a receiver-end chip. The transmitter-end chip includes a first port. The receiver-end chip includes a second port. The first port is connected to the second port, and an operating mode of the first port is different from an operating mode of the second port. When the transmitter-end chip is coupled to the receiver-end chip without through another chip, the transmitter-end chip determines a first target address of the receiver-end chip with respect to the transmitter-end chip according to the operating mode of the first port, and transfers a command to the receiver-end chip according to the first target address, such that the receiver-end chip executes the command.

A method for electronic device identifier assignment at a host computing device includes receiving a current local identifier of a separate electronic device and a full unique identifier of the separate electronic device. A host-specific identifier is assigned to the separate electronic device by, based at least in part on determining that the current local identifier of the separate electronic device is included in a set of local identifier values available for assignment, assigning the host-specific identifier to the separate electronic device with a same local identifier value as the current local identifier. Based at least in part on determining that the current local identifier of the separate electronic device is already assigned by the host computing device to a different separate electronic device, the host-specific local identifier is selected from the set of local identifier values available for assignment and assigned to the separate electronic device.

A slave device includes: a serial communications slave having an address designated for performing serial communications with a master; a single address determination pin configured to be, selectively, connected to a power terminal without being connected to a first external resistor, connected to a ground terminal without being connected through a second external resistor, connected to the power terminal through the first external resistor, or connected to the ground terminal through a second external resistor; and an address allocator configured to designate the address of the serial communications slave based on a plurality of state bits determined depending on a connection state of the single address determination pin.

Dynamic address allocation of multiple device instances of an improved inter-integrated circuit (I3C) target device by an I3C controller device is disclosed. A first device instance is configured to receive a command and a clock signal from the I3C controller device, and further receive a first status signal that is indicative of a first device instance ID of the first device instance. The first device instance is further configured to decode the command based on the first status signal and the clock signal, and generate a response that includes the first device instance ID. The I3C controller device is configured to allocate a dynamic address to the first device instance based on the response. The first device instance is then configured to generate and provide a second status signal to a second device instance for facilitating dynamic address allocation of the second device instance.

A device for a single wire digital bus, includes an interface for the bus configured to receive a request to arbitrate for an address and to transmit device specific data on the bus upon receipt of the request to arbitrate for an address The device further includes a control circuit configured to determine, if a further device transmits device specific data on the bus, and to use the address arbitrated for, if no further device transmits device specific data on the bus.

A system of electronic modules is described, along with a method of assigning addresses to the modules. The modules are communicatively connected along a communication path, and are also communicatively connected to an address bus. Adders are positioned along the address bus, with at least one adder located between each pair of modules. When any module is assigned an address, its adjacent adder will increment the address and assign the incremented address to the next-adjacent module.