A switched mode power supply comprises a communication interface including an address terminal configured to couple to an external resistor for setting a communication address of the switched mode power supply. A control circuit is configured to determine the value of the external resistor a first time with a first technique and set the communication address of the switched mode power supply based on the value of the external resistor determined using the first technique if the value of the external resistor is greater than the threshold value. The control circuit is also configured to, if the value of the external resistor is less than the threshold value, determine the value of the external resistor a second time with a second technique and set the communication address of the switched mode power supply based on the value of the external resistor determined using the second technique.

An apparatus in various embodiments is for use in a local area network and includes a discernment logic circuit and logic circuitry. The discernment logic circuit discerns whether a requested communications transaction received over the management communications bus from another of the logic nodes involves a first type of transaction or a second type of transaction, the second type of transaction having a plurality of commands associated with the requested communications transaction to convey respectively different parts of the requested communications transaction including an address part and a data part. The logic circuitry disables, in response to a reset of an address pointer in the one of the plurality of logic nodes and the requested communications transaction being the second type of transaction, the address pointer to mitigate a likelihood that the requested communications transaction is performed via the communication protocol while the address pointer for the second type of transaction is erroneous.

In one aspect, an electronic device includes a switching circuit connected to a resistance circuit and ground, the resistance circuit connected to a port and the port configured to be connected in series to an external resistor and a supply voltage. A voltage at the port is a first voltage that is less than the supply voltage if the switching circuit is enabled to be a closed circuit and the voltage at the port is a second voltage that is equal to the supply voltage if the switching circuit is enabled to be an open circuit.

A position-sensing method and device for sensing the installation location (F1, . . . , Fi) of slave units (SE1, . . . , SEi) in an operating region (A1, . . . , Ai) of a system (A) comprising a number i of adjacent operating regions (A1, . . . , Ai) each having a slave unit, wherein the individual slave units (SE1, SEi) have a changeable operating function for achieving or changing the physical state in the operating region in question of the system, and wherein a respective sensor (S1, . . . , Si) is provided in each operating region in question in order to sense a measurement variable (T) proportional to the physical state in the operating region in question and an evaluating device is provided in order to determine, upon the activation or changing of the operating function of at least one slave unit (SE1, . . . , SEi), the installation location (F1, . . . , Fi) of said slave unit from the change in the measurement variables (T) over time.

A circuit includes a set of LED driver devices and a controller including a set of nodes coupled to a first slave address pin and a second slave address pin in each LED driver devices in the set of LED driver devices. Each LED driver device includes a finite state machine (FSM) configured to generate LED drive PWM-modulated signal patterns, an oscillator configured to generate a clock signal for the FSM, a first signal path activatable between the first slave address pin and the FSM, and a second signal path activatable between the FSM and the second slave address pin.

An apparatus and method are provided for handling address decoding in a system-on-chip (SoC). The SoC has processing circuitry for performing data processing operations, a first plurality of devices, and an interconnect to couple the processing circuitry to the first plurality of devices. The first plurality of devices are a first level of devices within a hierarchical structure of devices forming a device network. Those devices communicate using a device communication protocol which also provides an enumeration mechanism to enable software executed on the processing circuitry to discover and configure the devices within the network. The system address space provides a pool of addresses that are reserved for allocation to the first plurality of devices. An address decoder of the SoC has a device address decoder to maintain, for each device in the first plurality of devices, an indication of which addresses within the pool are allocated to that device. Hence, when a request is issued by the processing circuitry identifying an address within the pool of addresses, the device address decoder can be used to determine the appropriate device within the first plurality of devices that the request is directed to. The device address decoder is exposed to the software as a device of the device network so as to enable the software executing on the processing circuitry to discover and configure the device address decoder using the enumeration mechanism. As a result, the allocation of the pool of addresses amongst the first plurality of devices can be dynamically reconfigured under software control.

A single communication interface between a master device and at least one slave device and a method with internal/external addressing mode using the single communication interface. In the single communication interface between a master device and at least one slave device, the master device includes a master interface and the slave device comprises a slave interface and a slave bus-system, whereas the slave interface is directly connected to the slave bus-system, wherein the master interface and the slave interface communicate on a packet based protocol by an internal and external addressing mode inside the slave interface, whereas the addressing mode, data transfer direction and data address location are coded by the packet based protocol inside a first 32-bit word of each transmission between the master device and slave device over the single communication interface.

Disclosed is a power management integrated circuit with embedded address resolution protocol functionality. In one embodiment, a device is disclosed comprising a data storage device; and an address resolution protocol (ARP) state machine communicatively coupled to the data storage device and included within a power management integrated circuit (PMIC), the ARP state machine configured to assign an address to the data storage device and validate requests for data stored in the data storage device received over a bus.

Various embodiments of the present technology may provide methods and system for an integrated circuit. The system may provide, at most, two integrated circuits (i.e., slave devices) connected to and configured to communicate with a host device (i.e., a master device). At least one of integrated circuits may comprise a first interface and a second interface, wherein the second interface is connected to the host in a manner that is opposite that of the first interface.

A circuit includes a set of LED driver devices and a controller including a set of nodes coupled to a first slave address pin and a second slave address pin in each LED driver devices in the set of LED driver devices. Each LED driver device includes: a finite state machine (FSM) configured to generate LED drive PWM-modulated signal patterns; an oscillator configured to generate a clock signal for the FSM; a first signal path activatable between the first slave address pin and the FSM; and a second signal path activatable between the FSM and the second slave address pin.