A semiconductor device, referred to herein as a Globally Interconnected Operations (GIO) layer, provides global operations in the form of global data reduction for one or more PE arrays. The GIO layer includes processing elements that perform global data reduction on processing results from one or more PE arrays. The GIO layer includes connectors that allow it to be arranged in a 3D stack with one or more PE arrays, for example, on top of or beneath a PE array. This allows reduction operations to be implemented across PE arrays using an efficient topology with superior flexibility, scalability, latency and/or power characteristics that is customizable for particular use cases at assembly time, without requiring costly and time-consuming redesign of PE arrays, and without being constrained by particular PE array designs.

This disclosure is directed to dynamic power management of a device interface based on a desired bandwidth for transporting data by the device interface. A device interface may packetize and transport raw data to a processor core complex or a peripheral device. In different embodiments, the peripheral device or the processor core complex may generate the raw data. The peripheral device and/or the processor core complex may increase or decrease a data bandwidth of the device interface for transporting the data. In different cases, the peripheral device or the processor core complex may dynamically activate and deactivate a different number of data links of the device interface based on dynamically determining the desired bandwidth. The peripheral device and/or the processor core complex may reduce a power consumption of the device interface by dynamically deactivating one or more of the data links based on the desired bandwidth being below the data bandwidth of the activated data links.