Technologies for dynamic accelerator selection include a compute sled. The compute sled includes a network interface controller to communicate with a remote accelerator of an accelerator sled over a network, where the network interface controller includes a local accelerator and a compute engine. The compute engine is to obtain network telemetry data indicative of a level of bandwidth saturation of the network. The compute engine is also to determine whether to accelerate a function managed by the compute sled. The compute engine is further to determine, in response to a determination to accelerate the function, whether to offload the function to the remote accelerator of the accelerator sled based on the telemetry data. Also the compute engine is to assign, in response a determination not to offload the function to the remote accelerator, the function to the local accelerator of the network interface controller.

Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to semiconductor interconnects, such as on-package die-to-die (D2D) interconnects, for example. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.

Systems, methods, and apparatus are described for communicating virtual GPIO (VGI) information between multiple source devices and multiple consuming devices. A method for facilitating communication of VGI state over a serial bus includes determining that an in-band interrupt has been asserted on the serial bus while the serial bus is idle, participating in an exchange of VGI state when a first bit of a device address transmitted during bus arbitration associated with the in-band interrupt has a first value, receiving a plurality of bits of VGI state during the exchange of VGI state, including bits transmitted by multiple devices coupled to the serial bus, and mapping at least one bit in the plurality of bits of VGI state to a physical GPIO pin. Transmission of at least a second bit of the device address is suppressed when the first bit of a device address has the first value.

An apparatus includes a first memory and a direct memory access (DMA) controller. The DMA controller includes a second memory to store the received packet and a third memory, and receives a packet including a header where information for DMA is registered and data to be stored in the first memory. The DMA controller acquires and stores, in the third memory, the header and a beginning portion of a given length from beginning of the data of the packet stored in the second memory. The DMA controller reads the data included in the packet from the third memory when it is determined, based on the header, that a data length of the data included in the packet is less than or equal to the given length, and performs storage of the read data by DMA in the first memory.

Technologies for providing remote access to a shared memory pool include a memory sled. The memory sled includes a memory pool having one or more byte-addressable memory devices and a memory pool controller coupled to the memory pool. The memory pool controller is to produce, for each of a plurality of compute sleds, address space data indicative of addresses of byte-addressable memory in the memory pool accessible to the compute sled, and corresponding permissions associated with the addresses. The memory pool controller is also to provide the address space data to each corresponding compute sled and receive, from a requesting compute sled of the plurality of compute sleds, a memory access request. The memory access request includes an address from the address space data to be accessed. The memory pool controller is also to perform, in response to receiving the memory access request, a memory access operation on the memory pool. Other embodiments are also described and claimed.

Technologies for efficiently managing the allocation of memory in a shared memory pool include a memory sled. The memory sled includes a memory pool of byte-addressable memory devices. The memory sled also includes a memory pool controller coupled to the memory pool. The memory pool controller receives a request to provision memory to a compute sled. Further, the memory pool controller maps, in response to the request, each of the memory devices of the memory pool to the compute sled. The memory pool controller additionally assigns access rights to the compute sled as a function of one or more memory characteristics of the compute sled. The memory characteristics are indicative of an amount of memory in the memory pool to be used by the compute sled and the access rights are indicative of access permissions to one or more memory address ranges associated with the one or more memory devices.

An apparatus includes a first memory and a direct memory access (DMA) controller. The DMA controller includes a second memory to store the received packet and a third memory, and receives a packet including a header where information for DMA is registered and data to be stored in the first memory. The DMA controller acquires and stores, in the third memory, the header and a beginning portion of a given length from beginning of the data of the packet stored in the second memory. The DMA controller reads the data included in the packet from the third memory when it is determined, based on the header, that a data length of the data included in the packet is less than or equal to the given length, and performs storage of the read data by DMA in the first memory.

A transfer apparatus has an input port and an output port, an input line speed of the input port and an output line speed of the output port being capable of being set to differ from each other. The transfer apparatus comprises, for each output port: a low-latency frame transmission buffer to store a low-latency frame received at the input port; a normal-latency frame transmission buffer to store a normal-latency frame that is a frame received at the input port, the normal-latency frame being permitted to be transferred with higher latency than the low-latency frame; a time calculation unit to calculate output start time of the low-latency frame by using information on a frame length of the low-latency frame, the input line speed, and the output line speed when the low-latency frame is received; and an output contention control unit to control transfer of the low-latency frame and the normal-latency frame by using the output start time.

Implementations of the disclosure implement timely and context triggered (TACT) prefetching that targets particular load IPs in a program contributing to a threshold amount of the long latency accesses. A processing device comprising an execution unit; and a prefetcher circuit communicably coupled to the execution unit is provided. The prefetcher circuit is to detect a memory request for a target instruction pointer (IP) in a program to be executed by the execution unit. A trigger IP is identified to initiate a prefetch operation of memory data for the target IP. Thereupon, an association is determined between memory addresses of the trigger IP and the target IP. The association comprising a series of offsets representing a path between the trigger IP and an instance of the target IP in memory. Based on the association, an offset from the memory address of the trigger IP to prefetch the memory data is produced.

Systems, methods, and apparatus are described that enable single-cycle pre-emption on a serial bus. An apparatus is coupled to a serial bus through a bus interface and includes a controller configured to provide a clock signal on the first line of the serial bus, transmit data on a second line of the serial bus in accordance with timing provided by the clock signal, cause the line driver to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line, detect a first pulse on the clock signal while the line driver is in the high impedance state, cause the line driver to exit the high impedance state prior to transmitting a second edge in the clock signal, and initiate bus arbitration after detecting the first pulse. The first edge and the second edge may transition in opposite directions.