Devices and techniques for short-thread rescheduling in a processor are described herein. When an instruction for a thread completes, a result is produced. The condition that the same thread is scheduled in a next execution slot and that the next instruction of the thread will use the result can be detected. In response to this condition, the result can be provided directly to an execution unit for the next instruction.

An information handling system includes a printed circuit board, a z-axis compression connector, and a compression attached memory module (CAMM). The compression connector coupled receives a first memory channel and a second memory channel from the PCB. The CAMM receives the first memory channel and the second memory channel from the first compression connector. The CAMM is configured to provide memory transaction on only the first memory channel.

Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory controller with various memory devices. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at the memory controller coupled to memory devices.

The present disclosure relates to techniques for facilitating communication and memory transfer between PCIe devices that permit access to an entire address space even though a limited address space is exposed and/or visible via the PCIe BAR registers. To this end, the present disclosure aims to permit memory transfer of large blocks of memory from one device to another including memory invisible to the system (i.e. not exposed via PCIe BAR registers). For example, in some embodiments, a data packet may be received at a port associated with a processor interconnect. The data packet includes a header which contains a first address associated with the port. In response to identifying the first address from the first data packet at the port, the data packet is decoded. During the decoding process, a second address is identified in a payload of the data packet. The second address corresponds to a first memory location, and data associated with the payload of the data packet is then stored to the first memory location.

A circuit system includes a processing integrated circuit die comprising a first die-to-die interface circuit and a memory interface circuit. The circuit system also includes a second integrated circuit die comprising a second die-to-die interface circuit and a compute circuit that performs computations for the processing integrated circuit die. The first and the second die-to-die interface circuits are coupled together. The compute circuit is coupled to exchange information with the memory interface circuit through the first and the second die-to-die interface circuits.

A processing device in a memory sub-system retrieves an input/output (IO) instruction of a plurality of IO instructions from an IO instruction memory in the memory sub-system, the IO instruction comprising a first number of bits. The processing device further generates an IO vector based on the IO instruction, the IO vector comprising a second number of bits, wherein the second number of bits is greater than the first number of bits. In addition, the processing device causes a plurality of IO signals, based on the IO vector, to be driven on a signal communication bus to a memory device in the memory sub-system, wherein the plurality of IO signals comprises a number of signals equal to the second number of bits of the IO vector.

An apparatus comprises at least one processing device comprising a processor coupled to memory. The at least one processing device is configured to obtain an input-output request issued by an application executing on a compute node via at least one network and to identify a storage node as corresponding to the obtained input-output request based at least in part on the obtained input-output request. The at least one processing device is configured to associate information corresponding to the compute node with the input-output request and to submit the input-output request and the associated information that corresponds to the compute node to the storage node via the at least one network. The storage node is configured to submit a response to the input-output request to the compute node via the at least one network based at least in part on the information.

Secure circuitry detects a number of memory transactions matching a specified pattern on a bus between a processor external to the secure circuitry and a memory external to the secure circuitry. The secure circuitry detects a cumulative size of the memory transactions matching the specified pattern on the bus between the processor and the memory. In response to either or both of the number of the memory transactions being outside a number range and the cumulative size being outside a size range, the secure circuitry performs an action.

An embodiment method of accessing a memory for reading and/or writing data comprises generating a memory transaction request comprising a burst of memory access requests towards a set of memory locations in the memory, the memory locations having respective memory addresses. The method further comprises transmitting via an interconnect bus to a memory controller circuit coupled to the memory a first signal conveying the memory transaction request and a second signal conveying information for mapping the burst of memory access requests onto respective memory addresses of the memory locations in the memory. The method further comprises computing, as a function of the information conveyed by the second signal, respective memory addresses of the memory locations, and accessing the memory locations to read data from the memory locations and/or to write data into the memory locations.

Disclosed in some examples, are methods, systems, devices, and machine readable mediums that store instructions for programmable atomic transactions in a memory of the programmable atomic unit prior to execution of the programmable atomic transaction. The memory in some examples may be an instruction RAM. The memory in some examples may be partitioned into partitions of a fixed size that stores a same number of instructions. Each programmable atomic transaction may use one or more contiguously located instruction partitions. By loading the instructions ahead of time, the instructions are ready for execution when the transaction is requested.