Provided are a PCIe interrupt processing method and apparatus, a device and a non-transitory readable storage medium, relating to the technical field of computers. The PCIe interrupt processing method comprises: a currently generated internal interrupt signal is acquired; a PCIe interrupt type supported by a current FPGA is determined according to an interrupt vector signal output by a PCIe IP core, so as to determine a corresponding target interrupt processing mechanism according to the PCIe interrupt type; and the internal interrupt signal is processed by means of the target interrupt processing mechanism, and a processing result is input to the PCIe IP core, such that the PCIe IP core sends an interrupt message packet to a central processing unit on the basis of the processing result. The technical solution expands the compatibility of an FPGA with processor interrupts, facilitating the implementation of FPGA logic platform construction.

An apparatus comprises a plurality of interfaces, each couplable to a respective one of a plurality of processing circuitries either in a higher criticality compliance state or a lower criticality compliance state. Each interface can receive from its respective processing circuitry interrupt signals destined to a target processing circuitry of the plurality of processing circuitries and transmit to its respective processing circuitry interrupt signals issued by a source processing circuitry of the plurality of processing circuitries. Control circuitry monitors the flow of the interrupt signals and determines whether the flow of interrupt signals exhibits a discrepancy with respect to an expected flow of interrupt signals, and performs a mitigation action in respect of said discrepancy to avoid violation of the higher criticality compliance state.

Embodiments of apparatuses, methods, and systems for virtualization of interprocessor interrupts are disclosed. In an embodiment, an apparatus includes a plurality of processor cores; an interrupt controller register; and logic to, in response to a write from a virtual machine to the interrupt controller register, record an interprocessor interrupt in a first data structure configured by a virtual machine monitor and send a notification of the interprocessor interrupt to at least one of the plurality of processor cores.

In some aspects, a system may transmit, via a main device of the system, a first value of a chip select signal indicating chip select de-assertion. The system may transmit, via a target device of the system, an interrupt signal while the chip select line indicates the first value. The system may transmit, via the main device and via the chip select line, a second value of the chip select signal indicating chip select assertion. The system may perform, via at least one of the one or more data lines, one or more data operations based on the target device transmitting the interrupt signal. Numerous other aspects are described.

An apparatus comprises a plurality of interfaces, each couplable to a respective one of a plurality of processing circuitries either in a higher criticality compliance state or a lower criticality compliance state. Each interface can receive from its respective processing circuitry interrupt signals destined to a target processing circuitry of the plurality of processing circuitries and transmit to its respective processing circuitry interrupt signals issued by a source processing circuitry of the plurality of processing circuitries. Control circuitry monitors the flow of the interrupt signals and determines whether the flow of interrupt signals exhibits a discrepancy with respect to an expected flow of interrupt signals, and performs a mitigation action in respect of said discrepancy to avoid violation of the higher criticality compliance state.

The present disclosure relates to an apparatus and a method for processing input/output completion of a storage device. The apparatus includes: an input/output command generation unit that generates an input/output command for the storage device: an input/output completion checking method determination unit that provides an input/output request to the storage device based on the input/output command and determines an input/output completion checking method for the storage device; and an input/output completion determination unit that performs an input/output checking procedure according to the input/output completion checking method and determines whether the input/output command is completed. Therefore, the present disclosure may dynamically switch to the most advantageous technique for detecting I/O completion of the storage device, depending on CPU contention arising from CPU sharing of an I/O request process, and may improve I/O performance by quickly detecting the I/O completion of the storage device.

A method may include identifying an application operable to submit one or more commands to a data transform accelerator. The method may also include determining one or more classes of service utilized with at least one bank of data transform engines in the data transform accelerator. The method may further include estimating a workload to be transmitted to the data transform accelerator. In response to the workload satisfying a threshold and interrupt control being enabled in the at least one bank of data transform engines, the method may also include configuring interrupt control for the one or more classes of service.

Provided are a PCIe interrupt processing method and apparatus, a device and a non-transitory readable storage medium, relating to the technical field of computers. The PCIe interrupt processing method comprises: a currently generated internal interrupt signal is acquired; a PCIe interrupt type supported by a current FPGA is determined according to an interrupt vector signal output by a PCIe IP core, so as to determine a corresponding target interrupt processing mechanism according to the PCIe interrupt type; and the internal interrupt signal is processed by means of the target interrupt processing mechanism, and a processing result is input to the PCIe IP core, such that the PCIe IP core sends an interrupt message packet to a central processing unit on the basis of the processing result. The technical solution expands the compatibility of an FPGA with processor interrupts, facilitating the implementation of FPGA logic platform construction.

Aspects of the disclosure relate to power management of a system-on-chip (SoC) and techniques of optimizing system performance and power management through power limits coordination via a low latency bus interface that provides a flexible protocol which enables high priority messages to facilitate power management. The protocol enables shallow power mitigation techniques to reduce the need of full mitigation of the apparatus.

In some aspects, a system may transmit, via a main device of the system, a first value of a chip select signal indicating chip select de-assertion. The system may transmit, via a target device of the system, an interrupt signal while the chip select line indicates the first value. The system may transmit, via the main device and via the chip select line, a second value of the chip select signal indicating chip select assertion. The system may perform, via at least one of the one or more data lines, one or more data operations based on the target device transmitting the interrupt signal. Numerous other aspects are described.