A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.

Provided is a multi-master collision prevention system including: a plurality of functional blocks including a plurality of external modules and a plurality of internal modules performing different functions; a plurality of interfaces respectively connected to the plurality of external modules, respectively; a plurality of dedicated registers including priority information of the plurality of functional blocks and connected to the plurality of functional blocks, respectively; a common block selectively connected to the plurality of functional blocks, and configured to function as a master for controlling the common blocks when the plurality of functional blocks are connected to the common block; and a priority determination unit configured to determine a connection between any one of the plurality of functional blocks and the common block.

A device includes a first interface unit connected to a first controller area network (CAN) bus, a second interface unit connected to a second CAN bus, and a control unit configured to identify, in a case where transmission of a CAN frame is started, a CAN bus detected to be in a dominant state first after end of arbitration from the first CAN bus or the second CAN bus, as a CAN bus to which a transmission source device of the CAN frame is connected.

Systems, methods, and apparatus are described for communicating virtual GPIO (VGI) information between multiple source devices and multiple consuming devices. A method for facilitating communication of VGI state over a serial bus includes determining that an in-band interrupt has been asserted on the serial bus while the serial bus is idle, participating in an exchange of VGI state when a first bit of a device address transmitted during bus arbitration associated with the in-band interrupt has a first value, receiving a plurality of bits of VGI state during the exchange of VGI state, including bits transmitted by multiple devices coupled to the serial bus, and mapping at least one bit in the plurality of bits of VGI state to a physical GPIO pin. Transmission of at least a second bit of the device address is suppressed when the first bit of a device address has the first value.

A memory request management system may include a memory device and a memory controller. The memory controller may include a read queue, a write queue, an arbitration circuit, a read credit allocation circuit, and a write credit allocation circuit. The read queue and write queue may store corresponding requests from request streams. The arbitration circuit may send requests from the read queue and write queue to the memory device based on locations of addresses indicated by the requests. The read credit allocation circuit may send an indication of an available read credit to a request stream in response to a read request from the request stream being sent from the read queue to the memory device. The write credit allocation circuit may send an indication of an available write credit to a request stream in response to a write request from the request stream being stored at the write queue.

An example multi-node system that prevents multi-master issues on a common bus is disclosed. The system has a first node and a second node. A backplane is coupled to the first and second nodes via a system management bus. A complex programmable logic device is coupled to the system management bus. The complex programmable logic device includes hardware logic operable to arbitrate between bus commands from the first and second nodes.

Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

An embodiment of an apparatus includes a retry queue circuit, a transaction arbiter circuit, and a plurality of transaction buffers. The retry queue circuit may store one or more entries corresponding to one or more memory transactions. A position in the retry queue circuit of an entry of the one or more entries may correspond to a priority for processing a memory transaction corresponding to the entry. The transaction arbiter circuit may receive a real-time memory transaction from a particular transaction buffer. In response to a determination that the real-time memory transaction is unable to be processed, the transaction arbiter circuit may create an entry for the real-time memory transaction in the retry queue circuit. In response to a determination that a bulk memory transaction is scheduled for processing prior to the real-time memory transaction, the transaction arbiter circuit may upgrade the bulk memory transaction to use real-time memory resources.

In a device comprising a serial bus and a plurality of devices, register/address mappings and/or unique group identifiers are used to convey additional information in messages/datagrams over the serial bus without explicitly sending such information in the message/datagram. Such register/address mappings may be done beforehand, and in conjunction with group-specific identifiers, may reduce transmission latency by keeping the size of the messages/datagrams small. Since all devices on the serial bus have prior knowledge of such register/address mappings and/or group-specific identifiers, recipient devices are able to infer information from the group-specific identifiers and/or register/address sent in each message/datagram that is not explicitly sent within such message/datagram.

A method for a slave bus and a master bus includes receiving a first frame via a first data channel, wherein the first frame includes at least first header data, first payload data and first checksum. The method further includes implementing a function depending on the header data contained in the received first frame, and generating a second frame including second header data, second payload data, which are determined by the implemented function, and a second checksum. The second checksum is ascertained at least on the basis of the second payload data and the first header data contained in the received first frame. The method also includes transmitting the second frame via a second data channel simultaneously with receiving the first frame via the first data channel.