Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control.

A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC includes a processor of the SoC including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus, the deadlock controller being configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and extract, via the second bus, state information of the isolated processor in the deadlock state.

A device includes a first interface unit connected to a first controller area network (CAN) bus, a second interface unit connected to a second CAN bus, and a control unit configured to identify, in a case where transmission of a CAN frame is started, a CAN bus detected to be in a dominant state first after end of arbitration from the first CAN bus or the second CAN bus, as a CAN bus to which a transmission source device of the CAN frame is connected.

Techniques for round robin bus arbitration are disclosed. A plurality of bus requesters is coupled to a common bus by an arbitration logic. Bus access requests are stored in a request vector (RV). A grant history vector (GHV) that contains the last granted requester is checked. A relative request vector (RRV) is created by performing N circular shifts in a right direction until the last granted requester occupies a first bit position in the RRV. The RRV is examined for the first asserted bit beginning with a second bit position in the first direction. A one-hot encoded relative grant vector (RGV) is generated based on the first asserted bit in the RRV. A grant vector (GV) is produced by executing N circular shifts of the RGV in a left direction. Access is granted to the bus requester indicated by the GV.