A brake demand arbitrating device is provided comprising: a first transceiver configured to receive a first brake demand generated by a first brake pedal of a vehicle; a second transceiver configured to receive a second brake demand generated by a second brake pedal of the vehicle; a processor configured to determine which of the first brake demand and the second brake demand is greater; and a third transceiver configured to send the greater brake demand to a brake controller of the vehicle. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

A serial connector adapter system includes a serial connector adapter device connected to a computing device. The serial connector adapter device includes a serial communication request subsystem coupled to a serial connector and a first USB connector. The computing device includes a second USB connector connected to the first USB connector, a serial communication subsystem coupled to the second USB connector, and a serial communication configuration subsystem coupled to the second USB connector and the serial communication subsystem. The serial communication configuration uses a USB ground drain connection in the first and second USB connectors subsystems to identify the serial connector adapter device and perform bi-directional communications to receive a request for serial communications with the serial communication subsystem and, in response, configures the serial communication subsystem to perform serial communications via the serial connector using USB transmitter/receiver pair connections in the first and second USB connectors.

A system on a chip (SoC) with a Universal Asynchronous Receiver/Transmitter (UART) interface includes a UART interface circuit, a detection circuit, and a control circuit. The UART interface circuit includes: a plurality of UART signal pads for receiving and transmitting signals; and a UART voltage pad for receiving an external operating voltage. The detection circuit is configured to detect the magnitude of the external operating voltage and thereby generate a detection result. The control circuit is configured to determine setting of a supply voltage for the plurality of UART signal pads according to the detection result. The control circuit makes the setting of the supply voltage be compatible with the external operating voltage according to the detection result, wherein the external operating voltage is a lower first voltage or a higher second voltage, and the first lower voltage is equal to an internal device operating voltage of the SoC.

Please substitute the new Abstract submitted herewith for the original Abstract:

An electrical controller includes a first interface via which data are able to be transferred, a second interface, separate from the first interface, via which data are able to be transferred, a control unit, and an operating mode memory for storing operating mode information. The control unit is configured to operate the controller in a first safety-oriented operating mode or in a second safety-oriented operating mode depending on the stored operating mode information.

The disclosed computer-implemented method for controlling auxiliary device access to computing devices based on device functionality descriptors may include (i) detecting a connection of an auxiliary device to a client computing device, (ii) receiving a set of functionality descriptors from the auxiliary device, each functionality descriptor of the set of functionality descriptors identifying a separate functionality of the auxiliary device, (iii) determining whether the set of functionality descriptors matches a set of reference descriptors, and (iv) performing a security action based on the determination of whether the set of functionality descriptors matches the set of reference descriptors. Various other methods, systems, and computer-readable media are also disclosed.

A brake demand arbitrating device is provided comprising: a first transceiver configured to receive a first brake demand generated by a first brake pedal of a vehicle; a second transceiver configured to receive a second brake demand generated by a second brake pedal of the vehicle; a processor configured to determine which of the first brake demand and the second brake demand is greater; and a third transceiver configured to send the greater brake demand to a brake controller of the vehicle. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, comprising: continuously monitoring data frames and/or control frames from a second side; and triggering a TX (transmission) data rate adjustment when information of the data frame and/or the control frame indicates that the lowest layer of the second side detects errors from received data.

A system on a chip (SoC) with a Universal Asynchronous Receiver/Transmitter (UART) interface includes a UART interface circuit, a detection circuit, and a control circuit. The UART interface circuit includes: a plurality of UART signal pads for receiving and transmitting signals; and a UART voltage pad for receiving an external operating voltage. The detection circuit is configured to detect the magnitude of the external operating voltage and thereby generate a detection result. The control circuit is configured to determine setting of a supply voltage for the plurality of UART signal pads according to the detection result. The control circuit makes the setting of the supply voltage be compatible with the external operating voltage according to the detection result, wherein the external operating voltage is a lower first voltage or a higher second voltage, and the first lower voltage is equal to an internal device operating voltage of the SoC.

This disclosure describes systems, methods, and devices related to priority packet optimization. A device may receive a trigger indicating a switch to a high priority data transfer based on a clock signal remaining at a predetermined logic value for a defined number of unit intervals. The device may transmit a priority vector from a transmitter to a receiver, the priority vector comprising a plurality of bits, wherein a bit is transmitted during a respective clock cycle and a clock toggles during transmission. The device may receive a trigger indicating a resumption of a previous data transfer based on the clock signal again remaining at the predetermined logic value for the defined number of unit intervals. The device may format the priority vector as a sideband packet comprising an opcode and reserved fields before forwarding to upper protocol layers.

The present invention provides a mainband training method between a transmitter within a first die and a receiver within a second die, wherein the mainband training method comprises the steps of: setting, by the receiver, a valid framing criteria and a valid signal pass criteria, wherein the valid framing criteria is more lenient than the valid signal pass criteria; receiving, by the receiver, a valid signal from the transmitter, and determining if the valid signal satisfies the valid framing criteria; and if the valid signal satisfies the valid framing criteria, identifying, by the receiver, centers of eye opening of multiple data signal and the valid signal.