An integrated circuit device is provided. In some examples, the integrated circuit device includes a first amplifier path, a second amplifier path coupled in parallel with the first amplifier path, a matching network coupled to the first amplifier path and the second amplifier path, and an antenna coupled to the matching network. In some such examples, the first amplifier path includes a first differential power amplifier coupled to the matching network, and the second amplifier path includes a second differential power amplifier coupled to the matching network. The integrated circuit device may further include a controller coupled to selectively enable the first amplifier path to provide a transmitter output power within a first range and to selectively enable the second amplifier path to provide a transmitter output power within a second range that is different from the first range.

A MLU-based magnetic device including a plurality of MLU-based magnetic cells, each MLU cell including a first ferromagnetic layer having a first magnetization, a second ferromagnetic layer having a second magnetization, and a spacing layer between the first and second ferromagnetic layers. An input device is configured for generating an input signal adapted for changing the orientation of the first magnetization relative to the second magnetization and vary a resistance of the MLU device. A bit line is configured for passing a sense signal adapted for measuring the resistance. A processing unit is configured for computing an electrical variation from the sense signal and outputting an electrical variation signature. The present disclosure further pertains to an authentication method for reading the MLU device.

A MLU-based magnetic device including a plurality of MLU-based magnetic cells, each MLU cell including a first ferromagnetic layer having a first magnetization, a second ferromagnetic layer having a second magnetization, and a spacing layer between the first and second ferromagnetic layers. An input device is configured for generating an input signal adapted for changing the orientation of the first magnetization relative to the second magnetization and vary a resistance of the MLU device. A bit line is configured for passing a sense signal adapted for measuring the resistance. A processing unit is configured for computing an electrical variation from the sense signal and outputting an electrical variation signature. The present disclosure further pertains to an authentication method for reading the MLU device.

A system for hyper-dimensional computing for inference tasks may be provided. The device comprises an item memory for storing hyper-dimensional item vectors, a query transformation unit connected to the item memory, the query transformation unit being adapted for forming a hyper-dimensional query vector from a query input and hyper-dimensional base vectors stored in the item memory, and an associative memory adapted for storing a plurality of hyper-dimensional profile vectors and for determining a distance between the hyper-dimensional query vector and the plurality of hyper-dimensional profile vectors, wherein the item memory and the associative memory are adapted for in-memory computing using memristive devices.

Analog multipliers circuits can provide signal processing asynchronously and clock free and with low power consumptions, which can be advantageous, including in emerging mobile, portable, and at edge or near sensor artificial intelligence (AI) and machine learning (ML) applications. As such, analog multipliers can process signals memory-free in AI and ML applications, which avoids the power consumption and latency delays attributed to memory read-write cycles in conventional AI and ML digital processors. Based on standard digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of multi-quadrant current-mode analog multiplier (iMULT) circuits that can be utilized in current-mode multiply-accumulate (iMAC) circuits and artificial neural network (ANN) end-applications that require high-volumes, low costs, medium precision, low power consumptions, and clock free asynchronous signal processing.

Analog multipliers circuits can provide signal processing asynchronously and clock free and with low power consumptions, which can be advantageous, including in emerging mobile, portable, and at edge or near sensor artificial intelligence (AI) and machine learning (ML) applications. As such, analog multipliers can process signals memory-free in AI and ML applications, which avoids the power consumption and latency delays attributed to memory read-write cycles in conventional AI and ML digital processors. Based on standard digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of multi-quadrant current-mode analog multiplier (iMULT) circuits that can be utilized in current-mode multiply-accumulate (iMAC) circuits and artificial neural network (ANN) end-applications that require high-volumes, low costs, medium precision, low power consumptions, and clock free asynchronous signal processing.

A power amplifier includes a distributor distributing an input first signal to a second signal and a third signal delayed by about 2 degrees (45<<90) from the second signal, a first amplifier amplifying the second signal and outputting a fourth signal when a first-signal power level is not lower than a first level, a second amplifier amplifying the third signal and outputting a fifth signal when the first-signal power level is not lower than a second level that is greater than the first level, a first phase shifter receiving the fourth signal and outputting a sixth signal delayed by about degrees from the fourth signal, a second phase shifter receiving the fifth signal and outputting a seventh signal advanced by about degrees from the fifth signal, and a combiner combining the sixth and seventh signals and outputting an amplified signal of the first signal.

A power amplification module includes a first amplification transistor that receives a first signal outputs an amplified second signal from the collector thereof; and a bias circuit that supplies a bias current to the base of the first amplification transistor. The first bias circuit includes a first transistor that is diode connected and is supplied with a bias control current; a second transistor that is diode connected, the collector thereof being connected to the emitter of the first transistor; a third transistor, the base thereof being connected to the base of the first transistor, and the bias current being output from the emitter thereof; a fourth transistor, the collector thereof being connected to the emitter of the third transistor and the base thereof being connected to the base of the second transistor; and a first capacitor between the base and the emitter of the third transistor.

A power amplification module includes: a first bipolar transistor in which a radio frequency signal is input to a base and an amplified signal is output from a collector; a second bipolar transistor that is thermally coupled with the first bipolar transistor and that imitates operation of the first bipolar transistor; a third bipolar transistor in which a first control voltage is supplied to a base and a first bias current is output from an emitter; a first resistor that generates a third control voltage corresponding to a collector current of the second bipolar transistor at a second terminal; and a fourth bipolar transistor in which a power supply voltage is supplied to a collector, the third control voltage is supplied to a base, and a second bias current is output from an emitter.

A MLU-based magnetic device including a plurality of MLU-based magnetic cells, each MLU cell including a first ferromagnetic layer having a first magnetization, a second ferromagnetic layer having a second magnetization, and a spacing layer between the first and second ferromagnetic layers. An input device is configured for generating an input signal adapted for changing the orientation of the first magnetization relative to the second magnetization and vary a resistance of the MLU device. A bit line is configured for passing a sense signal adapted for measuring the resistance. A processing unit is configured for computing an electrical variation from the sense signal and outputting an electrical variation signature. The present disclosure further pertains to an authentication method for reading the MLU device.