Patent classifications
G06J1/02
Hybrid analog-digital matrix processors
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
Hybrid analog-digital matrix processors
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
Device with a plurality of clock domains
In an embodiment a device includes a first circuit configured to send a signal comprising numbers successively separated by a constant value to at least one second circuit, each second circuit being in a clock domain different from a clock domain of the first circuit and at least one third circuit configured to determine whether the successive numbers of the signal received by the second circuit are separated by the constant value, wherein the signal is sent to a respective third circuit in each of the clock domains different from the clock domain of the first circuit.
HYBRID ANALOG-DIGITAL MATRIX PROCESSORS
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
HYBRID ANALOG-DIGITAL MATRIX PROCESSORS
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
HYBRID ANALOG-DIGITAL MATRIX PROCESSORS
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
HYBRID ANALOG-DIGITAL MATRIX PROCESSORS
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
Hybrid analog-digital matrix processors
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
Hybrid analog-digital matrix processors
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
Quantum Computer System and Method for Partial Differential Equation-Constrained Optimization
A computer (such as a classical computer, a quantum computer, or a hybrid quantum-classical computer) which performs PDE-constrained optimization of problems in cases in which, for a fixed {right arrow over (w)}, there is an explicit expression for {right arrow over (s)} that is either optimal or an approximation to the optimal solution. This enables embodiments of the present invention to eliminate {right arrow over (s)} from the optimization problem and to formulate the optimization as a polynomial unconstrained binary optimization (PUBO) problem.