Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

A hybrid analog-digital architecture is presented. The hybrid analog-digital architecture is comprised of an adjacency memory, a global controller, an array of memory cells and a computing circuit. The adjacency memory is configured to store a graph representing an optimization problem. The array of memory cells is arranged in columns and rows. Each node of the graph is assigned to a memory cell in the array of memory cells and each memory cell is configured to store an electric charge representing a spin state of an Ising model. The computing circuit is interfaced with the array of memory cells. The computing circuit is configured to read current from a given pair of memory cells in the array of memory cells, compute a differential current between the currents read from the given pair of memory cells, compute an update charge for one of the memory cells in the given pair of memory cells using the differential current, and transfer the update charge to the one memory cell in the given pair of memory cells. The global controller is interconnected between the adjacency memory and the array of memory cells.

A hybrid analog-digital architecture is presented. The hybrid analog-digital architecture is comprised of an adjacency memory, a global controller, an array of memory cells and a computing circuit. The adjacency memory is configured to store a graph representing an optimization problem. The array of memory cells is arranged in columns and rows. Each node of the graph is assigned to a memory cell in the array of memory cells and each memory cell is configured to store an electric charge representing a spin state of an Ising model. The computing circuit is interfaced with the array of memory cells. The computing circuit is configured to read current from a given pair of memory cells in the array of memory cells, compute a differential current between the currents read from the given pair of memory cells, compute an update charge for one of the memory cells in the given pair of memory cells using the differential current, and transfer the update charge to the one memory cell in the given pair of memory cells. The global controller is interconnected between the adjacency memory and the array of memory cells.