Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block. A tile is a valid tile for a primitive block if at least one primitive in the primitive block intersects that tile.

Methods and apparatus to facilitate 3D object visualization and manipulation across multiple devices are disclosed. Example apparatus disclosed herein include a viewpoint determiner, a visible shard determiner, and a laminate assembler. The viewpoint determiner determines a viewpoint location of a viewpoint corresponding to a viewing device, the viewpoint location being in a reference frame of a three-dimensional (3D) model. The visible shard determiner determines a visible shard set of the 3D model based on the viewpoint location. The laminate assembler generates a two-dimensional (2D) image of the visible shard set.

Data gathered from a continual data source is converted into an image and represented by a rectilinear grid defining a grid of pixels. Each pixel in each axis unit of one axis is examined in parallel using a graphic processor unit (GPU) to determine whether any pixels exceed a predefined threshold. Those pixels that exceed the threshold are identified as positive return pixels. Within each axis unit groups of positive return pixels are identified based on a first axis epsilon. Adjacent groups of positive return pixels are assembled by merging the axis units based on a second axis epsilon. Groups of positive return pixels grouped together according to the first axis epsilon and the second axis epsilon are classified and reported as a signal.

Disclosed subject matter relates generally to predictive graphics processing for interactive content.

Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

A three-dimensional image player capable of real-time interaction is provided, including: a material management module, a rendering control module, an interaction control module, and a display control module; the material management module further includes an attribute parsing module for performing classification parsing on materials, the hardware environment, and the operating platform; the three-dimensional image player capable of real-time interaction, may use smart engine matching technology to match three-dimensional image of different formats and types with different engines, to realize the whole process capability of importing, rendering engine intelligent matching, loading, previewing, and interacting, and also it supports unique interactive experiences such as previewing, clicking, and effect presenting of three-dimensional image with interactive capabilities.

A mechanism is described for facilitating dynamic cache allocation in computing devices in computing devices. A method of embodiments, as described herein, includes facilitating monitoring one or more bandwidth consumptions of one or more clients accessing a cache associated with a processor; computing one or more bandwidth requirements of the one or more clients based on the one or more bandwidth consumptions; and allocating one or more portions of the cache to the one or more clients in accordance with the one or more bandwidth requirements.

Methods and tessellation modules for tessellating a patch to generate tessellated geometry data representing the tessellated patch. Received geometry data representing a patch is processed to identify tessellation factors of the patch. Based on the identified tessellation factors of the patch, tessellation instances to be used in tessellating the patch are determined. The tessellation instances are allocated amongst a plurality of tessellation pipelines that operate in parallel, wherein a respective set of one or more of the tessellation instances is allocated to each of the tessellation pipelines, and wherein each of the tessellation pipelines generates tessellated geometry data associated with the respective allocated set of one or more of the tessellation instances.

Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

Apparatus and method for compressing an acceleration data structure such as a bounding volume hierarchy (BVH). For example, one embodiment of a graphics processing apparatus comprises: one or more cores to execute graphics instructions including instructions to perform ray tracing operations; and compression circuitry to compress lowest level nodes of a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes, each of the lowest level nodes comprising pointers to leaf data; the compression circuitry to quantize the lowest level nodes to generate quantized lowest level nodes and to store each quantized lowest level node and associated leaf data without the pointers to the leaf data.