A method of handling signal transmission applicable to a display system includes a plurality of steps. The steps include transmitting a reset signal embedded in a first data signal to each of at least one source driver via a first data channel, generating a first control signal for setting the at least one source driver, and transmitting the first control signal embedded in a second data signal to each of the at least one source driver via a second data channel when the reset signal is transmitted via the first data channel.

A method of handling signal transmission applicable to a display system includes a plurality of steps. The steps include transmitting a reset signal embedded in a first data signal to each of at least one source driver via a first data channel, generating a first control signal for setting the at least one source driver, and transmitting the first control signal embedded in a second data signal to each of the at least one source driver via a second data channel when the reset signal is transmitted via the first data channel.

The disclosure discloses a timing controller board, a main control board, a display device and a detection method thereof. The timing controller board outputs a second level signal transmitted by a first fixed potential signal pin to the main control board through a detection circuit when a first data signal pin outputs a first level signal; the main control board loads a second potential signal transmitted by a second fixed potential signal pin to a second data signal pin and a clock signal pin through a switching circuit upon receiving the second level signal, to cause the main control board to stop sending a data signal to the timing controller board through the second data signal pin and stop sending a clock signal to the timing controller board through the clock signal pin.

A display system modifies display cycles of one or more displays to perform a system operation while avoiding visual perturbations at the one or more displays. The display system modifies, synchronizes, or both, blanking periods of the one or more displays such that blanking periods equal or exceed a blackout duration and overlap for at least the blackout duration. Then the system performs the system operation during an overlapping portion of the one or more blanking periods, where the system operation reduces availability of display data at the one or more displays.

A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.

A display system includes: a host processor which outputs first image data and outputs scan frequency information and a partial scan enable signal, based on an image driving frequency; a display module controlled by the host processor; and an interface. The display module includes: a display driving circuit which controls a selection of pixel rows to which the data signals are supplied based on the scan frequency information and the partial scan enable signal; and a display panel which displays an image on selected pixel rows based on the data signals. In a video mode of the interface, the host processor divides and outputs the first image data through the interface during transmission periods, based on the image driving frequency, and suspends an output of the first image data through the interface during suspend periods.

An display driver and an operating method of the display driver are provided. The display driver includes a receiver comprising a bias current control circuit. The receiver receives image data. The bias current control circuit computes a data bit rate of the image data, and adjusting a bias current of the receiver according to the data bit rate. The operating method is adapted to the display driver.

A timing controller includes a receiving circuit, a timing control circuit, and a plurality of insertion loss circuits. The receiving circuit is configured to receive N frames of signals. The timing control circuit is configured to: detect a bit error rate of an (M-1).sup.th-frame signal in a blanking interval of an M.sup.th-frame signal; adjust a swing of the (M-1).sup.th-frame signal according to a target swing value corresponding to the bit error rate of the (M-1).sup.th-frame signal; and select the corresponding insertion loss circuit according to the target swing value corresponding to the bit error rate of the (M-1).sup.th-frame signal, wherein M and N are both positive integers, and M is greater than 1 and less than or equal to N. The present disclosure is applied to signal adjustment of the timing controller.

A timing controller includes a receiving circuit, a timing control circuit, and a plurality of insertion loss circuits. The receiving circuit is configured to receive N frames of signals. The timing control circuit is configured to: detect a bit error rate of an (M-1).sup.th-frame signal in a blanking interval of an M.sup.th-frame signal; adjust a swing of the (M-1).sup.th-frame signal according to a target swing value corresponding to the bit error rate of the (M-1).sup.th-frame signal; and select the corresponding insertion loss circuit according to the target swing value corresponding to the bit error rate of the (M-1).sup.th-frame signal, wherein M and N are both positive integers, and M is greater than 1 and less than or equal to N. The present disclosure is applied to signal adjustment of the timing controller.

A video input interface receives input video data in a normal state. A control input interface receives character data for On Screen Display (OSD) in a setup state. An encoder encodes the character data and stores encoded compressed data in a memory in the setup state. A decoder receives an instruction signal designating the character data to be displayed, reads and decodes one piece of compressed data corresponding to the instruction signal from the memory, and reproduces the original character data in the normal state. A multiplexer superimposes character data on frame data and outputs the data.