The invention relates to a computer-implemented method for reducing video latency and computer program product thereto for a computer video processing system. Two separate threads, an input thread and an output thread, are created and configured to run simultaneously and independently from each other. The input thread is configured to process video input frames that may be split into a plurality of input slices. The output thread is configured to process video output frames. The video output frames may also be split into a plurality of output slices.

The invention relates to a computer-implemented method for reducing video latency and computer program product thereto for a computer video processing system. Two separate threads, an input thread and an output thread, are created and configured to run simultaneously and independently from each other. The input thread is configured to process video input frames that may be split into a plurality of input slices. The output thread is configured to process video output frames. The video output frames may also be split into a plurality of output slices.

The disclosure is related to a method and a system for detecting a video scan type. In the method, a first frame and a second frame are firstly extracted from a video. The scan lines of each frame can be divided into a top field and a bottom field. A first zipper index of the combination of the top field of the first frame and the bottom field of the second frame is obtained. Further, a second zipper index of the combination of the bottom field of the first frame and the top field of the second frame is also obtained. A zipper index difference between the first zipper index and the second zipper index is calculated and is provided to determine the video scan type as an interlaced-scan video or a progressive-scan video.

The disclosure is related to a method and a system for detecting a video scan type. In the method, a first frame and a second frame are firstly extracted from a video. The scan lines of each frame can be divided into a top field and a bottom field. A first zipper index of the combination of the top field of the first frame and the bottom field of the second frame is obtained. Further, a second zipper index of the combination of the bottom field of the first frame and the top field of the second frame is also obtained. A zipper index difference between the first zipper index and the second zipper index is calculated and is provided to determine the video scan type as an interlaced-scan video or a progressive-scan video.

A tiling display apparatus includes a plurality of display modules connected with one another to configure a tiling screen and display division images and a system chip configured to change a display position of each of the division images, based on module arrangement information about each of the plurality of display modules, wherein seam patterns are configured to be coupled with adjacent display modules are provided in border regions of each display module, and each display module obtains, as the module arrangement information, connection state information about the seam patterns.

A non-transitory computer readable medium causing a computer to execute a process, the process includes: acquiring coordinate information indicating a boundary between an operable region and an inoperable region in the operation screen of a server; acquiring, from an operating system of the computer, an arrangement coordinate of a first window displaying the operation screen of the server including a first mouse cursor; detecting positions of the operable region and the inoperable region from the acquired coordinate information and the acquired arrangement coordinate; and interrupting notifying the first window of a coordinate of a second mouse cursor when the coordinate of the second mouse cursor acquired from the operating system of the computer is included in the inoperable region.

Technologies for secure z-order enforcement include a computing device having a processor with secure enclave support. A secure enclave invokes an EBIND instruction with display programming information that includes a z-order enforcement policy indicating whether the secure enclave requests z-order enforcement for an overlay surface associated with the secure enclave. The processor generates wrapped programming information in response to invoking the EBIND instruction. An untrusted supervisor component such as a device driver invokes an UNWRAP instruction with the wrapped programming information. The processor unwraps the wrapped programming information and programs a display controller with the z-enforcement policy. The processor may read a z-order enforcement status register of the display controller to determine if an overlay surface is available. For z-order enforcement, the display controller composes the overlay surface associated with the secure enclave in front of all other overlay surfaces of the display controller. Other embodiments are described and claimed.

Processor displays avatar to move from a starting coordinate to first movement destination coordinates in accordance with each instruction in first instruction set. Processor records coordinates after movement by instructions in the first instruction set, as first group, in accordance with instruction included in the first instruction set. Processor returns avatar to the before starting movement coordinates and displays avatar. Processor displays avatar to move from the before starting movement coordinates to second movement destination coordinates in accordance with each instruction in second instruction set. Processor records coordinates after movement by instructions in the second instruction set.

A video input interface receives video data. An OSD circuit draws an on screen display (OSD) character on the video data. The visibility detector checks whether the visibility of the OSD character is good or poor. A determination criterion for the visibility dynamically changes in a manner that depends on a background of the OSD character.

According to one embodiment, a display device includes a first substrate, a second substrate, a liquid crystal layer, a first alignment film, a pixel electrode, and a common electrode. The liquid crystal layer is disposed between the first substrate and the second substrate. The first alignment film is provided on the first substrate to be in contact with the liquid crystal layer. The pixel electrode is provided on the first substrate and covered with the first alignment film. The common electrode provided on the first substrate to form a lateral electric field. The liquid crystal layer is driven at a frequency of 40 Hz or less. A time constant of the liquid crystal layer is larger than a time constant of the first alignment film.