A scan driver for a display device includes a plurality of stages outputting scan signals. A first stage of the plurality of stages includes first to sixth transistors connected to a first carry clock line, a carry line, a previous carry line, and a second carry clock line. In a first frame period, the second carry clock line is configured to receive a second carry clock signal having at least one pulse with substantially the same phase as at least one of first pulses of a first carry clock signal to be applied to the first carry clock line.

A display device includes: a substrate including a first pixel area, a second pixel area having a smaller area than the first pixel area and connected to the first pixel area, and a peripheral area surrounding the first pixel area and the second pixel area; a first pixel provided in the first pixel area and a second pixel provided in the second pixel area; a first line connected to the first pixel and a second line connected to the second pixel; a dummy part disposed in the peripheral area, overlapping at least one of the first line and the second line and providing a parasitic capacitance that compensates for a difference in a load value between the first line and the second line; and a power supply line provided in the first and second pixel areas. The dummy part includes an insulating layer having at least one contact hole.

A shift register unit and a driving method thereof, a gate driving circuit and a driving method thereof, and a display device are provided to improve a stability of the shift register unit. The shift register unit includes a first input circuit, a second input circuit, an output circuit, a first pull-down circuit, and a second pull-down circuit and further includes: a first pull-down control circuit configured to control a level of the first pull-down node; a second pull-down control circuit configured to output a voltage of the third voltage terminal to the first pull-down node under the control of the fifth voltage terminal; a third pull-down control circuit configured to control a level of the second pull-down node; and a fourth pull-down control circuit configured to output the voltage of the third voltage terminal to the second pull-down node under the control of the fourth voltage terminal.

A shift register unit and a method for driving the same, a gate driving circuit and a method for driving the same, and a display apparatus. The shift register unit includes: an input sub-circuit configured to transmit a signal at an input signal terminal to a first node under control of a voltage at a second node; a discharging control sub-circuit configured to transmit a signal at a first clock signal terminal to the second node under control of a voltage at the first node; a discharging sub-circuit configured to transmit a signal at a first constant voltage signal terminal to an output signal terminal under control of the voltage at the second node; and an output sub-circuit configured to transmit a signal at a second clock signal terminal to the output signal terminal under control of the voltage at the first node.

A system includes an electronic display panel that has a plurality of pixels configured to depict frames of image data. The electronic display also includes display driver circuitry configured to, for a first frame of image data representing first image content, modify a gate-to-source voltage of a transistor of a first pixel of the plurality of pixels to a content-dependent first gate-to-source voltage. Additionally, after modifying the gate-to-source voltage to the first gate-to-source voltage, the display driver circuitry is configured to program the first pixel by modifying the gate-to-source voltage to a gate-to-source programming voltage that differs from the first gate-to-source voltage and is based on image data associated with the pixel from the first frame of the image data. Furthermore, the display driver circuitry is configured to cause the plurality of pixels to emit light.

A shift register unit and a driving method thereof, a gate drive circuit and a display device. The shift register unit includes a first input circuit, an output circuit and a first output pull-down circuit. The first input circuit is configured to charge a pull-up node in response to a first clock signal and reset the pull-up node in response to the first clock signal; the output circuit is configured to output a second clock signal to an output terminal under a control of a level of the pull-up node; the first output pull-down circuit is configured to denoise the output in response to a third clock signal.

A micro light-emitting diode (LED) display panel is provided. The micro LED display panel includes a substrate and a driving layer. The driving layer is disposed on the substrate. The driving layer includes a micro LED and a photo sensor. When the micro LED emits light to a finger of a user, the photo sensor generates a sensing signal.

A shift register circuit includes a noise reduction sub-circuit and a pull-down node control sub-circuit. A control end of the noise reduction sub-circuit is connected to a pull-down node, the noise reduction sub-circuit is connected to a first voltage input end. The pull-down node control sub-circuit includes a first pull-down node control sub-circuit and a second pull-down node control sub-circuit. The second pull-down node control sub-circuit controls the pull-down control node to be connected to a first clock signal input end when the first clock signal input end inputs a first level, the pull-down node to be connected to the first clock signal input end when a potential of the pull-down control node is at the first level, so that the potential of the pull-down node is at a first level and a noise reduction transistor included in the noise reduction sub-circuit is turned off.

In an array substrate, an electronic paper display panel and a drive method thereof, and a display device, a display area includes multiple sub-display areas. A plurality of scanning lines in each sub-display area are electrically insulated from each other, corresponding scanning lines in different sub-display areas are electrically connected to each other and display time of each sub-display area is controlled through control signal lines. When a control chip and a flexible circuit board are employed, only a small number of control chips and/or flexible circuit boards, or even only one control chip and/or one flexible circuit board, may drive multiple sub-display areas to display pictures.

A stage circuit including: a first sub-stage circuit coupled to a first input terminal receiving an input signal, a second input terminal receiving a first clock signal, and a third input terminal receiving a second clock signal, the first sub-stage circuit controlling a voltage of a first node, a second node, and a third node based on the input signal and the first and second clock signals, and supplying a first scan signal to a first output terminal based on the voltage of the second and third nodes; and a second substage circuit coupled to the second input terminal, a fourth input terminal receiving a third clock signal, and the first and second nodes, the second sub-stage circuit supplying a second scan signal to a second output terminal based on the first and third clock signal, and the voltage of the first and second nodes.