An LED display module, a display apparatus, and a method for controlling the LED display module and the display apparatus are provided. The LED display module includes a plurality of first LEDs arranged in a first line and a plurality of second LEDs arranged in a second line; a plurality of source interfaces, each of which is commonly connected to an anode of a corresponding one of the plurality of first LEDs and a cathode of a corresponding one of the plurality of second LEDs arranged in the same column as the corresponding one of the plurality of first LEDs; and a gate interface commonly connected to a cathode of each of the plurality of the first LEDs and an anode of each of the plurality of the second LEDs.

A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.

A display device includes a power supply to supply a first initialization power source to the pixels through a first initialization and to supply a second initialization power source to the pixels through a second power line.

Provided are a gate driver and a control method thereof. The gate driver receives a power down control signal corresponding to a power down mode, controls an operation of a gate signal processor using the power down control signal which is activated in response to the power down mode, and provides a gate high voltage or gate low voltage for a display panel in response to the power down control signal.

A image display medium driving device includes a voltage application unit that applies a voltage between a pair of substrates, at least one of which is transparent, of an image display medium including plural types of particles which are sealed between the pair of substrates, are attached to the substrates, and start to be separated from the substrates at different times when a predetermined voltage is applied and a control unit that controls the voltage application unit such that a time when the voltage is applied between the pair of substrates varies depending on image information.

A shift register unit includes an input circuit, a first control circuit, a second control circuit and an output circuit. The input circuit is configured to provide signals of the signal input terminal to the first control node, and provide signals of the first power supply terminal or the first clock signal terminal to the second control node. The first control circuit is configured to provide signals of the second power supply terminal or the second clock signal terminal to the first output terminal. The second control circuit is configured to provide signals of the first power supply terminal to the second output terminal. The output circuit is configured to provide signals of the second power supply terminal to the second output terminal.

A signal adjusting circuit and a display panel driving circuit are disclosed. The signal adjusting circuit includes an input terminal, a control terminal, an output terminal, a selection module and a delay module. The selection module is configured to selectively transfer an input signal received via the input terminal to the output terminal depending on an indication signal received via the control terminal. The delay module is configured to delay the input signal received from the selection module by an amount of time and transfer the delayed input signal to the output terminal. The display panel driving circuit includes one or more signal adjusting circuits to adjust periodic output enable pulses that enable outputting of gate scan pulses.

Disclosed are various aspects of a μ-LED or a μ-LED array for augmented reality or lighting applications, in particular in the automotive field. The μ-LED is characterized by particularly small dimensions in the range of a few μm.

A display device includes a scan write line for receiving a scan write signal, a first driving voltage line for receiving a first driving voltage, a first data line for receiving first data voltages, a second data line for receiving second data voltages, and a sub-pixel connected to the scan write line, the first data line, the second data line, and the first driving voltage line, wherein the sub-pixel includes a light emitting element connected to the first driving voltage line, a constant current generator configured to apply a driving current to the light emitting element according to a first data voltage among the first data voltages of the first data line, and a light emission period controller configured to control a light emission period of the light emitting element according to a second data voltage among the second data voltages of the second data line.

A shift register circuit includes a pull-up control sub-circuit, a pull-up sub-circuit and a shutdown auxiliary sub-circuit. The pull-up control sub-circuit is configured to transmit a voltage from the signal input terminal to the pull-up node under the control of the voltage from the signal input terminal. The shut-down auxiliary sub-circuit is configured to pull down a voltage of the pull-up node to a voltage of the discharge voltage terminal under the control of a voltage from the pull-up node. The pull-up sub-circuit is configured to transmit a voltage from the clock signal terminal to the first signal output terminal under the control of a voltage from the pull-up node. The first signal output terminal is configured to be connected to a gate line.