A gate driving circuit and a display panel are provided. The gate driving circuit includes a plurality of shift register units as cascaded, and the plurality of shift register units as cascaded includes a first shift register unit including a first clock signal terminal, an (n+1)-th shift register unit including an (n+1)-th clock signal terminal, a second shift register unit including a second clock signal terminal, and an (n+2)-th shift register unit including an (n+2)-th clock signal terminal. The gate driving circuit further includes a first clock signal line connected to the first clock signal terminal and the (n+1)-th clock signal terminal, and a second clock signal line connected to the second clock signal terminal and the (n+2)-th clock signal terminal.

A method for electromagnetic interference control and related devices are provided. The method includes the following. Electromagnetic interference between a Wi-Fi module and a MIPI of a display of the electronic device is detected in response to detecting a request for screen-projection to a target screen-projection device. In response to the detected electromagnetic interference, the display is turned off, and screen-projection to the target screen-projection device is performed, where the first prompt message indicates that the electronic device is turning off the display and performing screen-projection to the target screen-projection device.

Provided are a display control method and related products. The method includes: obtaining a target operating frequency of a modem in response to detecting that a target game initiates a game booster mode; obtaining a first MIPI operating frequency of a display MIPI bus; obtaining a target game frame rate of the target game in response to detecting the target operating frequency is interfered based on the first MIPI operating frequency; determining a target MIPI operating frequency range list corresponding to the target game frame rate; determining a second MIPI operating frequency having least interference on the target operating frequency of the modem from the plurality of MIPI operating frequencies in the target MIPI operating frequency range list; and adjusting a MIPI operating frequency of the display MIPI bus to the second MIPI operating frequency.

Provided are a display panel and a display device. The display panel includes multiple cascaded gate drive units. Each gate drive unit includes a shift register unit and an inverted unit. The inverted unit is electrically connected to the shift register unit. A scan output terminal of the shift register unit is electrically connected to one scan line. An inverted scan output terminal of the inverted unit is electrically connected to one inverted scan line. The scan output terminal of the shift register unit outputs a first effective pulse signal. The inverted scan output terminal of the inverted unit outputs a second effective pulse signal. A time period corresponding to the first effective pulse signal at least partially overlaps a time period corresponding to the second effective pulse signal, and the type of the first effective pulse signal is opposite to the type of the second effective pulse signal.

A display panel and a driving method thereof are provided, including a time schedule controller and at least one driver integrated circuit (driver IC). Pulse width modulation (PCM) data between the time schedule controller and the driver IC is transmitted in a decoded manner, and pulse amplitude modulation (PAM) data is transmitted in an undecoded manner, reducing a transmission rate between the time schedule controller and the driver IC, and thereby reducing or eliminating risks of electromagnetic interference (EMI). Furthermore, using this transmission method can reduce the number of latches used in the driver IC.

A gate driving circuit and a display panel are provided. The gate driving circuit includes a plurality of shift register units as cascaded, and the plurality of shift register units as cascaded includes a first shift register unit including a first clock signal terminal, an (n+1)-th shift register unit including an (n+1)-th clock signal terminal, a second shift register unit including a second clock signal terminal, and an (n+2)-th shift register unit including an (n+2)-th clock signal terminal. The gate driving circuit further includes a first clock signal line connected to the first clock signal terminal and the (n+1)-th clock signal terminal, and a second clock signal line connected to the second clock signal terminal and the (n+2)-th clock signal terminal.

An example method includes programming, during non-emission periods of frames of a plurality of frames based on image data of the frames, pixels of the plurality of pixels of a display of a computing device; causing, during emission periods of the frames, pixels of the plurality of pixels to emit light, wherein an amount of light emitted by the pixels during an emission period of a particular frame is based on the programming for the particular frame; and synchronizing operation of one or more sensors and operation of the plurality of pixels by at least causing the one or more sensors to alternatingly emit, through the display, electromagnetic radiation during emission periods and non-emission periods.

An example method includes programming, based on image data of a frame of a plurality of frames and during a non-emission period of the frame, pixels of a plurality of pixels of a display of a computing device; causing pixels of the plurality of pixels to emit light during an emission period of the frame, wherein an amount of light emitted by the pixels during the emission period is based on the programming; and synchronizing operation of one or more sensors and operation of the plurality of pixels by at least causing the one or more sensors to emit, during a particular portion of the emission period of the frame, electromagnetic radiation through the display.

A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.

A display panel is provided. The display panel includes a display part; and a fanout part. The display part includes a plurality of pixel driving circuits. The fanout part includes a bendable portion and a multiplexer. The display panel includes a plurality of first signal lines extending through the bendable portion, and connecting the plurality of pixel driving circuits to the multiplexer. A direct current supply line extending through the bendable portion and electrically connected to the plurality of pixel driving circuits. A portion of the direct current supply line is between the multiplexer and the bendable portion and crosses over the plurality of first signal lines.