A display device includes a first processor, a second processor, and a display module. The first processor is configured to: acquire version information of the second processor upon completion of startup of the second processor; determine version information of the corresponding first processor based on version information of the second processor; load a second configuration file corresponding to the version information of the first processor to output a second display screen associated with the second configuration file to the display module. The display module is configured to display the second display screen.

The present application discloses method for real-time processing image data based on a rendering engine. The method includes sampling a first set of data in a first pixel arrangement to be displayed as an image in a display screen with pixels in a second pixel arrangement. The method further includes creating a first model mapped with the first set of data to generate a second set of data and a second model mapped with the first set of data to generate a third set of data. Additionally, the method further includes rendering the second set of data using a first shader to output a fourth set of data and rendering the third set of data using a second shader to output a fifth set of data. Furthermore, the method includes superimposing the fourth set of data over the fifth set of data to display a sixth set of data.

An electronic device includes first and second processors, and first and second display units. While the first and second processors cooperate with each other and perform a display operation including a time display, the first processor can be set to a normal mode, a low power mode in which a power consumption is lower than a power consumption in the normal mode, or a pause mode in which a power consumption is lower than the power consumption in the low power mode, and the first processor is stopped. In the normal or low power modes, the first processor controls such that the first display unit displays a time, and the second processor controls such that the second display unit does not display a time. In the pause mode, the first display unit is turned off, and the second processor controls such that the second display unit displays a time.

A system and method uses a two-dimensional graphics library to generate an image representation that can be used by a three-dimensional graphics library to render the image.

A display controller is provided. The display controller includes n field-programmable gate arrays (FPGAs) (n is an integer greater than 1). A respective one of the n FPGAs includes a first input circuit and an output circuit and a first process circuit connected between the first input circuit and the output circuit. The first input circuit is configured to receive a respective one first sub-image corresponding to the respective one of the n FPGAs. The n first sub-images are combined to form one frame of initial image. The first process circuit is configured to enhance image-resolution of the respective one first sub-image to obtain a respective one second sub-image and the output circuit is configured to deliver the respective one second sub-image corresponding to the respective one of the n FPGAs to a timing-controller.

In some examples, a main thread of a plurality of execution threads executing on a plurality of processing cores of at least one hardware-based processor of a network device may receive a request for information associated with network routes that meet one or more criteria. Each of the plurality of execution threads may process a respective routing information partition to generate respective displayable information associated with a respective subset of the network routes that meets the one or more criteria. The main thread may generate consolidated displayable information associated with the network routes that meet the one or more criteria based on the respective displayable information generated by each of the plurality of execution threads. The main thread may output the consolidated displayable information associated with the network routes that meet the one or more criteria for display at a display device.

The present disclosure discloses an image data transmission apparatus having synchronous data transmission mechanism. Output stage circuits respectively receive and store image data corresponding to a part of a display frame. A primary switch circuit is coupled to a primary output stage circuit of the output stage circuits so as to maintain a control voltage of a control terminal at a first level when a primary frame aligning signal having the latest timing is not received from the primary output stage circuit, and switches the control voltage to a second level when the primary frame aligning signal is received. The output stage circuits output the image data to an image data receiving apparatus to display the display frame synchronously when the output stage circuits receive the control voltage having the second level through voltage transmission paths having the same signal transmission time.

Video or graphics, received by a render engine within a graphics processing unit, may be segmented into a region of interest such as foreground and a region of less interest such as background. In other embodiments, an object of interest may be segmented from the rest of the depiction in a case of a video game or graphics processing workload. Each of the segmented portions of a frame may themselves make up a separate surface which is sent separately from the render engine to the display engine of a graphics processing unit. In one embodiment, the display engine combines the two surfaces and sends them over a display link to a display panel. The display controller in the display panel displays the combined frame. The combined frame is stored in a buffer and refreshed periodically. In accordance with another embodiment, video or graphics may be segmented by a render engine into regions of interest or objects of interest and objects not of interest and again each of the separate regions or objects may be transferred to the display engine as a separate surface. Then the display engine may transfer the separate surfaces to a display controller of a display panel over a display link. At the display panel, a separate frame buffer may be used for each of the separate surfaces.

A method and apparatus for generating a series of frames with aid of a synthesizer to offload graphics processing unit (GPU) rendering within an electronic device are provided. The method may include: utilizing a GPU to perform full-rendering to generate a first frame in a color buffer, for being output to a display panel and displayed on the display panel; utilizing the GPU to generate a set of metadata of at least one subsequent frame in a metadata buffer; and utilizing the synthesizer to synthesize said at least one subsequent frame according to previous frame information and the set of metadata of said at least one subsequent frame, to generate said at least one subsequent frame in the color buffer, for being output to the display panel and displayed on the display panel.

Systems and methods for super sampling and viewport shifting of non-real time 3D applications are disclosed. In one embodiment, a graphics processing unit includes a processing resource to execute graphics commands to provide graphics for an application, a capture tool to capture the graphics commands, and a data generator to generate a dataset including at least one frame based on the captured graphics commands and to modify viewport settings for each frame of interest to generate a conditioned dataset.