A system and method of adjusting a refresh rate to match a given remote desktop stream frame rate is described. The system may include a processing device to transmit, as a media stream, a portion of a remote desktop image with a frame rate that matches a refresh rate to a remote desktop client.

A device including a display screen including display pixels arranged in rows and in columns, including a first row and a first column. The device further includes a display screen control circuit configured to, in a first mode, start the display of a first image on the first row and on the first column and, in a second mode, start the display of a second image on one of the rows different from the first row and/or on one of the columns different from the first column.

A display device includes a display panel, a display driver integrated circuit and a driving control circuit. The display panel includes a plurality of pixels connected to a plurality of driving lines and a plurality of source lines. The display driver integrated circuit includes a driving control signal generator. The driving control signal generator generates a driving control signal based on display device information and pixel values corresponding to at least a portion of the plurality of rows among a plurality of previous pixel values of a previous frame and a plurality of present pixel values of a present frame. The driving control circuit selectively connects the display driver integrated circuit with each of the plurality of driving lines based on the driving control signal such that first driving signals provided to first driving lines among the plurality of driving lines are blocked.

Disclosed is a method and device for processing Image, and an image transmitting system. The method includes that: data to be transmitted are processed according to a first resolution to obtain first image data, wherein the image resolution represented by each row of image data in the first image data is the first resolution, and the first resolution is the maximum resolution set by a system; and the first image data is folded to obtain second image data, wherein the number of rows of the second image data is greater than that of the first image data, the image resolution represented by each row of image data in the second image data is a second resolution, and the second resolution is less than the first resolution.

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for parallelization of GPU composition with DPU topology selection. A processor may receive an indication of a plurality of application layers for composition at a first processor (e.g., a DPU) and a second processor (e.g., a GPU). The processor may select one or more first application layers of the plurality of application layers for attempted composition at the first processor and one or more second application layers of the plurality of application layers for composition at the second processor. The processor may transmit each of the one or more first application layers to the first processor for composition and each of the one or more second application layers to the second processor for composition.

Circuitry for adjusting luminance of a display device is provided. The circuitry includes a non-volatile memory array having a plurality memory cells configured to store luminance data of the display device, and a luminance adjusting circuit configured to receive image data to be displayed on the display device. The luminance adjusting circuit is coupled directly to the non-volatile memory array to receive the luminance data of the display device from the non-volatile memory array and adjust the image data based on the luminance data of the display device.

Systems, apparatuses, and methods for performing asynchronous memory clock changes on multiple displays are disclosed. From time to time, a memory clock frequency change is desired for a memory subsystem storing frame buffer(s) used to drive pixels to multiple displays. For example, when the real-time memory bandwidth demand differs from the memory bandwidth available with the existing memory clock frequency, a control unit tracks the vertical blanking interval (VBI) timing of a first display. Also, the control unit causes a second display to enter into panel self-refresh (PSR) mode. Once the PSR mode of the second display overlaps with a VBI of the first display, a memory clock frequency change, including memory training, is initiated. After the memory clock frequency change, the displays are driven by the frame buffer(s) in the memory subsystem at an updated frequency.

A method for driving electro-optic displays including a layer of electro-optic material disposed between a common electrode and a backplane including an array of pixel electrodes, each coupled to a pixel transistor. The method for driving includes apportioning a displayable region of the electro-optic display into N BRAID line groups, where each of the N BRAID line groups is associated with a frame buffer. The method also includes receiving first image data comprising optical state data for the entire displayable region of the electro-optic display, and sequentially writing subsets of the first image data to each of the N frame buffers, wherein each of the N frame buffers is written with data corresponding to the corresponding BRAID line group. The method also includes sequentially updating portions of the displayable region of the electro-optic display based on the data in each of the N frame buffers.

A graphics processing unit (GPU) of a processing system transmits pixel data for a frame to a display in a compressed burst, so that the pixel data is communicated at a rate that is higher than the rate at which the display scans out the pixel data to refresh the frame at a display panel. By transmitting pixel data for the frame in a compressed burst, the GPU shortens the time spent transmitting the pixel data and extends the time before the next frame of pixel data is to be transmitted. During the extended time before the next frame of pixel data is to be transmitted, the GPU saves power by placing portions of the processing system in a reduced power mode.

An apparatus, method, and computer readable medium that access a frame buffer of a graphics processing unit (GPU), analyze, in the frame buffer, a frame representing displayed data, based on the analyzed frame, identify a reference patch that includes an instruction to retrieve content, generate an overlay including an augmentation layer which includes the content, superimpose the overlay onto the displayed data such that the content is viewable while a portion of the base layer is obscured, detect a user input, determine a location of the user input in the augmentation layer, associate the location in the augmentation layer with a target location in the base layer, and associate, within memory, the target location with an operation such that the user input in the augmentation layer activates an input in the base layer.