DEVICE COMPRISING A DISPLAY SCREEN WITH LOW-CONSUMPTION OPERATING MODE

Abstract

A device including a display screen including display pixels arranged in rows and in columns, including a first row and a first column. The device further includes a display screen control circuit configured to, in a first mode, start the display of a first image on the first row and on the first column and, in a second mode, start the display of a second image on one of the rows different from the first row and/or on one of the columns different from the first column.

Claims

1. Device comprising a display screen comprising display pixels arranged in rows and in columns, including a first row and a first column, the device further comprising a display screen control circuit configured to, in a first mode, start the display of a first image on the first row and on the first column and, in a second mode, start the display of a second image on one of the rows different from the first row and/or on one of the columns different from the first column.

2. Device according to claim 1, comprising a shift register comprising a succession of memory cells, including a first memory cell, and a data delivery circuit configured to, in the first mode, deliver in series first image data relative to the first image to the first memory cell and, in the second mode, deliver in series second image data relative to the second image to one of the memory cells other than the first memory cell.

3. Device according to claim 1, comprising a first memory having a first binary message comprising first bits stored therein, each first bit being associated with one of the columns of the display screen, a single one of the first bits being in a first state, the other first bits each being in a second state.

4. Device according to claim 1, comprising a second memory having a second binary message comprising second bits stored therein, each second bit being associated with one of the rows of the display screen, a single one of the second bits being in a third state, the other second bits each being in a fourth state.

5. Device according to claim 1, wherein the second image comprises image pixels, the number of image pixels being smaller than the number of display pixels of the display screen.

6. Device according to claim 1, wherein each display pixel comprises a display circuit comprising light-emitting diodes and a light-emitting diode control circuit.

7. Device according to claim 6, wherein the control circuit of each display pixel is configured to receive a digital signal or an analog signal.

8. Device according to claim 1, wherein the circuit for controlling the display screen is configured to, in the second mode, start the display of a third image on one of the rows different from the row at which the display of the second image starts.

9. Method of controlling a display screen comprising display pixels arranged in rows and in columns, including a first row and a first column, the method comprising the steps of: in a first mode, starting the display of a first image on the first row and on the first column; and in a second mode, starting the display of a second image on one of the rows different from the first row and/or on one of the columns different from the first column.

10. Method according to claim 9, comprising, in the first mode, delivering in series, to a shift register, comprising a succession of memory cells, including a first memory cell, first image data relative to the first image onto the first memory cell and, in the second mode, second image data relative to the second image to one of the memory cells other than the first memory cell.

11. Method according to claim 9, comprising, in the second mode, the beginning of the display of a third image on one of the rows different from the row at which the display of the second image starts.

12. Device according to claim 2, comprising a first memory having a first binary message comprising first bits stored therein, each first bit being associated with one of the columns of the display screen, a single one of the first bits being in a first state, the other first bits each being in a second state.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The foregoing features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0022] FIG. 1A illustrates a step of a method of displaying an image on a display screen;

[0023] FIG. 1B illustrates another step of the display method;

[0024] FIG. 1C illustrates another step of the display method;

[0025] FIG. 1D illustrates another step of the display method;

[0026] FIG. 2 shows an embodiment of a display pixel of a display screen;

[0027] FIG. 3 illustrates the principle of the display of an image of decreased dimensions on a display screen;

[0028] FIG. 4 partially and schematically shows an embodiment of a device with a display screen having a low-power mode;

[0029] FIG. 5 partially and schematically shows a variant of the device shown in FIG. 4;

[0030] FIG. 6 partially and schematically shows an embodiment of the routing circuit of the device shown in FIGS. 4 or 5; and

[0031] FIG. 7 partially and schematically shows an embodiment of a circuit for the display of at least two images on a display screen in low-power mode.

DESCRIPTION OF THE EMBODIMENTS

[0032] Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail.

[0033] Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected or they can be coupled via one or more other elements. Further, a signal which alternates between a first constant state, for example, a low state, noted “0”, and a second constant state, for example, a high state, noted “1”, is called a “binary signal”. The high and low states of different binary signals of a same electronic circuit may be different. In practice, the binary signals may correspond to voltages or to currents which may not be perfectly constant in the high or low state.

[0034] In the following disclosure, unless otherwise specified, when reference is made to absolute positional qualifiers, such as the terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc., or to relative positional qualifiers, such as the terms “above”, “below”, “upper”, “lower”, etc., or to qualifiers of orientation, such as “horizontal”, “vertical”, etc., reference is made to the orientation shown in the figures. Unless specified otherwise, the expressions “around”, “approximately”, “substantially” and “in the order of” signify within 10%, and preferably within 5%.

[0035] A pixel of an image corresponds to the unit element of the image displayed by the display screen. When the display screen is a color image display screen, it generally comprises, for the display of each image pixel, at least three emission and/or light intensity regulation components, also called display sub-pixels, which each emit a light radiation substantially in a single color (for example, red, green, or blue). The superposition of the radiations emitted by the three display sub-pixels provides the observer with the colored sensation corresponding to the pixel of the displayed image. In this case, the assembly formed by the three display sub-pixels used for the display of a pixel of an image is called display pixel of the display screen.

[0036] The display of a video on a display screen comprises the display of successive images on the display screen, an image being also called a frame, at a display frequency, also called refreshment frequency, which generally varies between 50 Hz and 240 Hz.

[0037] FIGS. 1A to 1D illustrate successive steps of a method of displaying a frame on a display screen 10 of a display device 5. Display screen 10 comprises an array of display pixels Pix.sub.i,.sub.j arranged in M rows and in N columns, i being an integer varying from 1 to M and j being an integer varying from 1 to N. As an example, M is an integer which varies from 1 to 2,000 and N is an integer which varies from 1 to 4,000. As an example, in FIGS. 1A to 1D, M is equal to 5 and N is equal to 12.

[0038] Display device 5 further comprises a selection circuit SEL which is coupled to the display pixels Pix.sub.i,.sub.j of each row by at least one row electrode WLi, i varying from 1 to M. Display device 5 further comprises a data circuit COL coupled to the display pixels Pix.sub.i,j of each column electrode BL.sub.j, j varying from 1 to N. Data circuit COL may comprise a shift register 20 comprising N memory cells 22.sub.j, j varying from 1 to N, and a buffer memory 30 comprising N memory cells 32.sub.j, j varying from 1 to N.

[0039] Data circuit COL receives digital image signals DATA containing the information relative to the image pixels to be displayed. Each memory cell 22.sub.j and each memory cell 32.sub.j may store the digital image signals containing the information relative to a single display pixel. Selection circuit SEL and data circuit COL receive synchronization signals SYNC, for example, binary signals. A first synchronization signal may indicate, for each image pixel, the end of the transmission of the digital image signals DATA relative to this image pixel. A second synchronization signal may indicate, for each row of the frame to be displayed, the end of the transmission of the digital image signals DATA relative to this row. A third synchronization signal may indicate, for each frame to be displayed, the end of the transmission of the digital image signals DATA relative to this frame.

[0040] FIG. 2 shows an embodiment of a display pixel Pix.sub.i,.sub.j comprising a display circuit DISP with light-emitting diodes LED, and a control circuit COM, coupled to row electrode WLi and to column electrode BL.sub.j. Control circuit COM is configured to control the light-emitting diodes LED of display circuit DISP from the digital or analog image signals received from column electrode BL.sub.j when it receives an activation signal from row electrode WLi. Display screen 10 and display pixels Pix.sub.i,j may have the structures described in document WO 2019/016481 or WO 2019/016482.

[0041] Considering FIGS. 1A to 1D again, the digital image signals DATA relative to the image pixels to be displayed on the first row of display screen 10 are supplied in series to shift register 20, by first memory cell 22.sub.1, the delivery of the digital signals relative to a new image pixel to memory cell 22.sub.1 causing the shifting of the digital signals stored in memory cell 22.sub.j to the next memory cell 22.sub.j+1.

[0042] FIG. 1A schematically shows the digital image signals relative to an image pixel stored in the first memory cell 22.sub.1 of shift register 20. In FIG. 1B, all the digital image signals relative to the display pixels to be displayed on the first row of display screen 10 have been delivered in series to shift register 20 and the digital image signals stored in each memory cell 22.sub.j of shift register 20 have been loaded into the memory cell 32.sub.j of buffer memory 30. Further, the display pixels Pix.sub.1,j, j varying from 1 to N, of the first row have been activated by selection circuit SEL.

[0043] FIG. 1C shows the display pixels Pix.sub.1,j,j varying from 1 to N, of the first row displaying the image pixels corresponding to the digital image pixels stored in buffer memory 30 and transmitted, in digital or analog form, to display pixels Pix.sub.i,j by column electrodes BL.sub.1 to BL.sub.N. Preferably, display pixels Pix.sub.i,j keep on displaying the display pixels relative to the digital signals that they have received as long as they are not selected again by selection circuit SEL. Simultaneously, digital image signals relative to the display pixels to be displayed on the second row of display screen 10 are delivered in series to shift register 20.

[0044] In FIG. 1D, all the digital image signals relative to the display pixels to be displayed on the second row of display screen 10 have been delivered in series to shift register 20 and the digital image signals stored in shift register 20 have been loaded into buffer memory 30. The display pixels Pix.sub.2,j, with j varying from 1 to N, of the second row are then selected by selection circuit SEL. The previously-described steps are repeated until the M.sup.th row of display screen 10. Selection circuit SEL then receives a synchronization signal SYNC indicating the frame end and then selects again the first row of display screen 10 for the display of the next frame.

[0045] FIG. 3 illustrates an embodiment of a method of displaying an image IM of decreased dimensions, called reduced image IM hereafter, on display screen 10 in a low-power mode. Image IM is called reduced since the number of image pixels of image IM is smaller than the number of display pixels of display screen 10. More particularly, the number of rows of image pixels of image IM is smaller than the number M of rows of display screen 10 and/or the number of columns of image pixels of image IM is smaller than the number N of columns of display screen 10. According to an embodiment, selection circuit SEL is controlled to start the display of reduced image IM at a row of number K, indicated by arrow F1 in FIG. 3, other than the first row of display screen 10, and/or data circuit COL only delivers digital image signals from a column of number L, indicated by arrow F2 in FIG. 3, different from the first column of display screen 10. This advantageously enables to decrease the number of display pixels of the display screen to be activated for the display of an image in low-power mode.FIG. 4 partially and schematically shows an embodiment of a display device 40 with a low-power mode in the case where the image signals delivered to display pixels Pix.sub.i,.sub.j are digital signals and FIG. 5 partially and schematically shows a variant of display device 40 with a low-power mode in the case where the image signals delivered to display pixels Pix.sub.i,.sub.j are analog signals.

[0046] Display device 40 comprises all the elements of the display device 5 shown in FIG. 1A. In the case where the image signals delivered to display pixels Pix.sub.i,.sub.j are digital signals (FIG. 4), each memory cell 32.sub.j, j varying from 1 to N, of buffer memory 30 may be directly coupled to column electrode BL.sub.j. In the case where the image signals delivered to display pixels Pix.sub.i,.sub.j are analog signals (FIG. 5), each memory cell 32.sub.j, j varying from 1 to N, of buffer memory 30 may be coupled to column electrode BL.sub.j via a digital-to-analog converter 41.sub.j (DAC).

[0047] Display device 40 further comprises a memory 42, also called register, and a routing circuit 44 receiving as an input digital image signals DATA and delivering digital image signals DATA to one of memory cells 22.sub.1 to 22.sub.N of shift register 20 according to the signal stored in memory 42. According to an embodiment, memory 42 comprises N bits, B.sub.1 to B.sub.N, a single bit B.sub.j of memory 42 being at “1”, all the other bits of memory 42 being at “0”, and the rank j of the memory cell 22.sub.j having the digital image signals DATA delivered thereto is the same as the bit B.sub.j of memory 42 which is at “1”. Display device 40 further comprises a module 46 configured to receive a signal S.sub.COL representative of the first column of display screen 10 from which reduced image IM is to be displayed and configured to store in memory 42 a signal representative of signal S.sub.COL.

[0048] According to an embodiment, routing circuit 44 comprises N switches SW.sub.1 to SW.sub.N. Each switch SW.sub.j, j varying from 1 to N, couples an input node IN, receiving digital image signals DATA, to a terminal of switch SW.sub.j, the other terminal of switch SW.sub.j being coupled to memory cell 22.sub.j. Each switch SW.sub.j, j varying from 1 to N, is controlled by a control signal EN.sub.j delivered from the bit B.sub.j stored in memory 42. According to an embodiment, when bit B.sub.j is at “1”, signal EN.sub.j controls the turning-on of switch SW.sub.j and when bit B.sub.j is at “0”, signal EN.sub.j controls the turning-off of switch SW.sub.j. A single one of bits B.sub.1 to B.sub.N is at “1” so that a single one of switches SW.sub.1 to SW.sub.N is on. In FIG. 4, routing circuit 44 is described with N switches SW.sub.1 to SW.sub.N. However, routing circuit 44 may comprise less than N switches. As a variant, routing circuit 44 is configured to deliver digital image signals DATA only to one of memory cells 22.sub.j, j varying from 1 to Q, Q being an integer smaller than N.

[0049] According to another embodiment, memory 42 comprises a number nbits of bits such that N is smaller than number 2 raised to power nbits, for example, 16 bits, and the rank j of the memory cell 22.sub.j having digital image signals DATA provided thereto is stored in memory 42. Control signals EN.sub.j, j varying from 1 to N, are then delivered by logic circuits, not shown, based on the data stored in memory 42, so that switch SW.sub.j is on and all the other switches of routing circuit 44 are off.

[0050] Display device 40 further comprises a memory 48, also called register, selection circuit SEL being configured to select, for the display of the first row of a new frame, first the row of display screen 10 according to the signal stored in memory 48. According to an embodiment, memory 48 comprises M bits, B'.sub.1 to B'.sub.M, a single bit B'i of memory 48 being at “1”, all the other bits of memory 48 being at “0”, and the rank i of the row which is selected first is the same as the index of the bit B'i of memory 48 which is at “1”. In the same way as for memory 42, in another embodiment, memory 48 contains the rank i of the row which has been selected first. Selection circuit SEL comprises a module 50 configured to receive a signal of indication of the first row S.sub.ROW of display screen 10 to be selected and configured to store in memory 48 a message adapted to signal S.sub.ROW.

[0051] In a normal operating mode, where each displayed frame has the same dimensions as display screen 10, that is, the same number of image pixel rows as the number of display pixel rows of display screen 10 and the same number of image pixel columns as the number of display pixel columns of display screen 10, signal S.sub.ROW indicates that the row to be selected for the display of the first row of a new frame is the first row of display screen 10 and signal S.sub.COL indicates that the column of screen 12 from which each new frame is to be displayed is the first column of display screen 10.

[0052] In the low-power mode, where each displayed frame has dimensions smaller than those of display screen 10, the row of display screen 10, designated by signal S.sub.ROW, to be selected for the display of the first row of the frame may be different from the first row of display screen 10 and the column of display screen 10, designated by signal S.sub.COL, from which the frame should be displayed may be different from the first column of display screen 10.

[0053] FIG. 6 partially and schematically shows a more detailed embodiment of a portion of the shift register 20, of the routing circuit 44, and of the memory 42 shown in FIGS. 4 or 5. In this embodiment, each memory cell 22.sub.j, j varying from 1 to N, corresponds to a D-type flip-flop, three memory cells 22.sub.j-1, 22.sub.j, and 22.sub.j+1 being shown as an example in FIG. 6. Each flip-flop 22.sub.j comprises a data input D, two set inputs R and S, two complementary outputs, a single output Q being shown, and is rated by a clock signal CLK. The D input of memory cell 22.sub.j is coupled to the Q output of memory cell 22.sub.j-1. Further, each memory cell B.sub.j, with j varying from 1 to N, corresponds to a D-type flip-flop, three memory cells B.sub.j-1, B.sub.j, and B.sub.j+1 being shown as an example in FIG. 6. Each flip-flop B.sub.j comprises a D data input, two set inputs R and S, two complementary outputs, a single output Q being shown, and is rated by a clock signal CLK'. The D input of memory cell B.sub.j is coupled to the Q output of memory cell B.sub.j-1.

[0054] The truth table [Table 1] of each memory cell 22.sub.j and B.sub.j is the following:

TABLE-US-00001 S R D Q.sub.n+1 0 0 0 0 0 0 1 1 1 0 x 1 0 1 x 0 1 1 NA NA

[0055] Each switch SW.sub.j may be controlled by a signal EN.sub.j and is configured to couple input node IN to the D input of flip-flop SW.sub.j when signal EN.sub.j is at “1”. Signal EN.sub.j is delivered by the Q output of memory cell B.sub.j. A reset signal Reset is delivered to the R input of each memory cell B.sub.j, j varying from 2 to N, and to the S input of memory cell B.sub.1 (shown as an example by memory cell B.sub.j-1 in FIG. 6). This enables, during a reset step, the display of an image to start at the first column of the display screen by default. The information of the column of screen 10 from which each new frame should be displayed in the low-power mode is loaded into memory 42 via a LOAD input coupled to the D input of first memory cell B.sub.1.

[0056] In the embodiment previously described in relation with FIG. 5, memory cells 22.sub.j and B.sub.j are formed by D flip-flops. However, memory cells 22.sub.j and B.sub.j may be formed with other types of flip-flops or of logic latches.

[0057] In the previously-described embodiments, in the low-power mode, a single reduced image is displayed on display screen 10.

[0058] According to an embodiment, two or more than two reduced images, each having dimensions smaller than the dimensions of display screen 10, may be displayed on display screen 10 in low-power mode.

[0059] FIG. 7 shows an embodiment of a circuit 51 for delivering signals S.sub.ROW and S.sub.COL in the case where P reduced images are to be displayed on the display screen in low-power mode, P being an integer greater than or equal to 2, for example, varying from 2 to 10. Circuit 51 comprises a memory 52 having, for the k.sup.th reduced image with k varying from 1 to Q, data representative of the integral number Nb.sub.k of rows of the reduced image stored therein. Memory 52 delivers a signal Nb equal to one of values Nb.sub.k. Circuit 51 comprises a memory 54 having, for the k.sup.th reduced image with k varying from 1 to Q, data representative of the first row L.sub.k of display screen 10 at which the first row of the reduced image should be displayed stored therein. Memory 54 delivers signal S.sub.ROW equal to one of values L.sub.k. Circuit 51 comprises a memory 56 having, for the k.sup.th reduced image with k varying from 1 to Q, data representative of the first column C.sub.k of display screen 10 at which the first column of the reduced image should be displayed stored therein. Memory 56 delivers signal S.sub.COL equal to one of values C.sub.k.

[0060] According to an embodiment, each memory 52, 54, and 56 is controlled by a signal Shift_en. According to an embodiment, signal Shift_en is a binary signal. As an example, when signal Shift_en does not vary, the signals S.sub.ROW, S.sub.COL, and Nb delivered by memories 52, 54, and 56 are not modified, and when signal Shift_en switches from “0” to “1”, the signals S.sub.ROW, S.sub.COL, and Nb delivered by memories 52, 54, and 56 are modified. As an example, when memory 52 delivers signal Nb equal to value Nb.sub.k, with k smaller than Q, it may deliver signal Nb equal to value Nb.sub.k+.sub.1 on reception of a pulse of signal Shift_en. Further, when memory 54 delivers signal S.sub.ROW equal to value L.sub.k, with k smaller than Q, it may deliver signal S.sub.ROW equal to L.sub.k+.sub.1 on reception of a pulse of signal Shift_en. Further, when memory 56 delivers signal S.sub.COL equal to value C.sub.k, with k smaller than Q, it may deliver signal S.sub.COL equal to value C.sub.k+.sub.1 on reception of a pulse of signal Shift_en.

[0061] According to an embodiment, circuit 51 further comprises a counter 58 which increments a signal CPT and a module 60 receiving signals CPT and Nb, delivering signal Shift_en, and delivering a reset signal resetn to counter 58. Counter 58 increments signal CPT each time it receives an end-of-frame synchronization signal SYNC. According to an embodiment, module 60 is configured to compare counter CPT with the number Nb supplied by memory 52 and is configured to emit a pulse of signal Shift_en when signal CPT is equal to number Nb and to reset counter 58. Signals Nb, S.sub.ROW and S.sub.COL are thus modified for each new reduced image to be modified.

[0062] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants may be combined, and other variants will occur to those skilled in the art. Finally, the practical implementation of the described embodiments and variants is within the abilities of those skilled in the art based on the functional indications given hereabove.