Active control of LEDs, LED packages, and related LED displays by way of pulse wide modulation (PWM) is disclosed. Effective PWM frequencies for LEDs are increased by segmenting duty cycles in which LEDs are electrically activated within individual PWM periods. Segmented duty cycles may be provided by transforming or re-ordering a sequence in which control signals are provided to LEDs. As such, LEDs may be electrically activated and deactivated multiple times within each PWM period. Active electrical elements that are incorporated into one or more LED packages of an LED display may be capable of segmenting the duty cycle within each LED package. Active electrical elements may also be capable of receiving reset signals from a data stream to either initiate a reset action or pass the reset signals along to other active electrical elements of a display.

Disclosed herein is a data interface device of a display apparatus including a timing controller, encoding clock-embedded image data corresponding to a logic high period of a data enable signal and clock-embedded blank data corresponding to a logic low period of the data enable signal and transferring an encoded data transfer packet to a transfer line, and a source integrated circuit generating an internal clock based on the encoded data transfer packet received through the transfer line and selectively decoding the clock-embedded image data based on the internal clock, wherein a transition pattern of the clock-embedded blank data differs in a plurality of transfer lines.

The present embodiment provides a technology for sensing a common mode voltage in the positive line and negative line of a transmission line for image data and determining whether noise occurs in the image data transmitted through the transmission line by comparing the common mode voltage with a set reference voltage.

A handheld imaging device has a data receiver that is configured to receive reference encoded image data. The data includes reference code values, which are encoded by an external coding system. The reference code values represent reference gray levels, which are being selected using a reference grayscale display function that is based on perceptual non-linearity of human vision adapted at different light levels to spatial frequencies. The imaging device also has a data converter that is configured to access a code mapping between the reference code values and device-specific code values of the imaging device. The device-specific code values are configured to produce gray levels that are specific to the imaging device. Based on the code mapping, the data converter is configured to transcode the reference encoded image data into device-specific image data, which is encoded with the device-specific code values.

Disclosed is a display method of a display panel. The display panel includes two display screens arranged opposite to each other, and the display method of the display panel includes: acquiring a liquid crystal response duration of each display screen upon receiving image information to be displayed; taking a display screen having a shorter liquid crystal response duration as a first display screen, and taking a display screen having a longer liquid crystal response duration as a second display screen; and driving the second display screen to display, and delaying to drive the first display screen to display. A display device and a display panel are also disclosed. The display panel of the present application has a good display effect.

A display substrate has a display area and a peripheral area around the display area. The display substrate includes a plurality of sub-pixels arranged in an array in the display area, and an interface circuit, at least two serial-to-parallel converters and at least one display driver that are in the peripheral area. The interface circuit is configured to receive target data including a plurality of serial display data. A serial-to-parallel converter in the at least two serial-to-parallel converters is used to convert the plurality of serial display data into parallel display data. The serial-to-parallel converter is electrically connected to one display driver to provide the parallel display data to the display driver. The display driver is used to output display driving signals to a plurality of sub-pixels according to the parallel display data.

A DA conversion circuit includes a first DA conversion circuit unit corresponding to a higher bit, a second DA conversion circuit unit corresponding to a lower bit, a capacitance element provided between the first DA conversion circuit unit and the second DA conversion circuit unit, the first DA conversion circuit unit includes a capacitance element and a selection circuit, the second DA conversion circuit unit includes a capacitance element and a selection circuit, and the selection circuit supplies a potential VL or VPH to one end of the capacitance element, and the selection circuit supplies the potential VL or VPL to one end of the capacitance element. The potential VPL is different from the potential VPH, and for example, VPL>VPH.

A clock data recovery circuit includes the following elements: a phase detector for outputting a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump for adjusting a charge amount of a second node according to the phase adjustment signal; a first switch including one end coupled to the second node and including another end coupled to a third node; a second switch including one end which receives a bias voltage and including another end coupled to the third node; a capacitor including a first electrode coupled to the third node; third switches; and voltage control oscillators including control terminals coupled to the third node and including output terminals coupled to the first node through the third switches.

Disclosed is a multi-display apparatus including display modules and a sensor. Some of the display modules sequentially connected receive a signal from the sensor, and each of the display modules transmits signals including the signal from the sensor to a display module connected to a rear stage thereof. The display module connected to a final stage transmits the signal from the sensor to a control box. The control box includes a detector configured to detect whether signals from a plurality of transmission lines include a generated flag signal based on the signals including a signal from the sensor and a selector configured to select a transmission line detected as including the flag signal by the detector and set the selected transmission line as a channel for communication with the sensor.

A display system comprising a plurality of display controller circuits controlling a like number of independent segments of pixel drive circuits of a backplane. Each pixel drive circuit comprises a memory element and associated pixel drive circuitry. The segments of the backplane may be organized vertically. The word line for the memory cells of a first segment of pixel drive circuits passes underneath a second segment of pixel drive circuits without directly interacting with the pixel drive circuits of the second segment in order to reach the pixel drive circuits of the first segment. The plurality of display controller circuits operate asynchronously but are kept at the same frame rate by an external signal such as Vsync.