A semiconductor component includes a substrate including a plurality of source/drain implants in the form of rows and a charge storage structure disposed over the substrate. The charge storage structure includes at least three continuous layers including a first silicon oxide layer, a silicon nitride layer disposed on the first silicon oxide layer, and a second silicon oxide layer disposed on the silicon nitride layer. The semiconductor component further includes a plurality of gate structures in the form of columns disposed over the charge structure and extending perpendicular to the rows and further includes a radiation protection layer disposed over the charge storage structure and the plurality of gate structures. The radiation protection layer includes a radiation resistant material including boron having an isotope composition of at least 90% boron-11.

An apparatus may include a first inverter and a second inverter cross-coupled between a first node and a second node to store a signal state represented by complementary voltages at the first node and the second node. The apparatus may further include a first path defined by the second inverter that includes an impedance element to resist a flow of charge suitable to change the signal state. The apparatus may further include the first inverter and a third inverter selectively cross-coupled between the first node and the second node to store a received signal state represented by the complementary voltages at the first node and the second node responsive to an assertion of a write enable signal.

A memory array for storing odd and even data bits of data words in alternate sub-banks to reduce multi-bit error rate is disclosed. The memory array alternates odd data bits of a first plurality of data words in consecutive columns a first sub-bank of first and second memory banks and even data bits of the first plurality of data words in consecutive columns of a second sub-bank of the first and second memory banks. For example, the lowest bits of each of N data words are stored in a first N consecutive columns of a first sub-bank. The second bits of the N data words are stored in the next N consecutive columns of a second sub-bank. The N data bits in each of the bit positions of the N data words are interleaved in corresponding column mux sets. Alternating odd and even bits between sub-banks reduces multi-bit soft errors.

An integrated circuit device includes a plurality of memory cells each including a channel region, a first sub-word line, a second sub-word line, and a storage element. A word line driving circuit is configured to drive the first and sub-word lines. The word line driving circuit includes a PMOS transistor, an NMOS transistor, a keeping NMOS transistor, and a first keeping PMOS transistor. A negative voltage is applied to a source of the NMOS transistor, the negative voltage is applied to a source of the keeping NMOS transistor, the first sub-word line is connected to a source of the first keeping PMOS transistor, the second sub-word line is connected to a drain of the first keeping PMOS transistor, and a negative voltage is applied to a gate of the first keeping PMOS transistor.

Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.

Memory devices might include a controller for access of an array of memory cells and a differential storage device comprising a pair of gate-connected non-volatile memory cells, wherein the controller is configured to cause the memory device to obtain information indicative of a data value stored in a particular memory cell of the array of memory cells, program additional data to the particular memory cell, determine if a power loss to the memory device is indicated while programming the additional data to the particular memory cell, and, if a power loss to the memory device is indicated, selectively program one memory cell of the pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell.

The present disclosure provides bit cells with data redundancy according to various aspects. In certain aspects, a bit cell includes a first memory element coupled to a write bit line, and a first write-access switch coupled between the first memory element and a ground. The bit cell also includes a second memory element coupled to the write bit line, and a second write-access switch coupled between the second memory element and the ground. The bit cell further includes a read-access switch coupled between the first memory element and a read bit line, wherein a control input of the read-access switch is coupled to a read-select line.

A method for radiation hardening flash memory performs accelerated aging on the flash memory by program-erase (PE) cycling the flash memory. Such accelerated aging induces trap states in the tunnel oxide layer of the flash memory, which results in improved ionizing radiation tolerance. The number of cycles used to harden a given memory cell is optimally determined in order to limit effects of the radiation hardening on the reliability of the cell.

Upon detecting power loss during the process of programming multi-level cell (MLC) memory in a storage system, the storage system takes steps to prevent data loss. In one example, the controller sends a graceful shutdown command to the memory, in response to which the memory aborts the ongoing programming operation and stores data from data latches associated with unprogrammed memory cells in single-level cell (SLC) memory. The memory can also store data from programmed memory cells in the SLC memory. The data to be programmed in the MLC memory can be reconstructed prior to powering down the storage system or after the storage system is powered back up. The reconstructed data can then be programmed in the MLC memory.

According to one or more embodiments, an apparatus comprising a plurality of dice latches, dice latch control logic, and a plurality of data input logic is provided. The dice latches are coupled in parallel and latch respective data. The dice latch control logic receives a load control signal and a reset control signal, provides a reset signal and further provides first and second load signals to the dice latches. The reset signal is based on the reset control signal. The first and second load signals are based on the load control signal and the reset control signal. The data input logic each are coupled to a respective one of the dice latches. Each of the data input logic receives a precharge control signal and respective input data and further provides data and complementary data to the respective one of the dice latches.