Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a substrate, a first deck including first memory cell strings located over the substrate, a second deck including second memory cell strings and located over the first deck, first data lines located between the first and second decks and coupled to the first memory cell strings, second data lines located over the second deck and coupled to the second memory cell strings, and first and second circuitries. The first and second data lines extending in a direction from a first portion of the substrate to a second portion of the substrate. The first buffer circuitry is located in the first portion of the substrate under the first memory cell strings of the first deck and coupled to the first data lines. The second buffer circuitry is located in the second portion of the substrate under the first memory cell strings of the first deck and coupled to the second data lines.

A read-out circuit and a read-out method for a three-dimensional memory, comprises a read reference circuit and a sensitive amplifier, the read reference circuit produces read reference current capable of quickly distinguishing reading low-resistance state unit current and reading high-resistance state unit current. The read reference circuit comprises a reference unit, a bit line matching module, a word line matching module and a transmission gate parasitic parameter matching module. With respect to the parasitic effect and electric leakage of the three-dimensional memory in the plane and vertical directions, the present invention introduces the matching of bit line parasite parameters, leakage current and transmission gate parasitic parameters into the read reference current, and introduces the matching of parasitic parameters of current mirror into the read current, thereby eliminating the phenomenon of pseudo reading and reducing the read-out time.

A memory device includes an array of 2T1C DRAM cells and a memory controller. The DRAM cells are arranged as a plurality of rows and columns of DRAM cells. The memory controller is internal to the memory device and is coupled to the array of DRAM cells. The memory controller is capable of receiving commands input to the memory device and is responsive to the received commands to control row-major access and column-major access to the array of DRAM cells. In one embodiment, each transistor of a memory cell includes a terminal directly coupled to a storage node of the capacitor. In another embodiment, a first transistor of a memory cell includes a terminal directly coupled to a storage node of the capacitor, and a second transistor of the 2T1C memory cell includes a gate terminal directly coupled to the storage node of the capacitor.

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.

The present disclosure relates to a memory component for a System-on-Chip (SoC) structure including at least a memory array and at least a logic portion for interacting with the memory array and with the SoC structure wherein the memory component is a structurally independent semiconductor device coupled to and partially overlapping the SoC structure.

A semiconductor device includes a memory mat having: a plurality of memory cells; a sense amplifier connected to a memory cell selected from the plurality of memory cells; a first power supply wiring; a first switch connected between the sense amplifier and the first power supply wiring and made an ON state in operating the sense amplifier; and a second switch connected to the sense amplifier and made an ON state in operating the sense amplifier, a second power supply wiring arranged outside the memory mat and connected to the first power supply wiring, a third power supply wiring arranged outside the memory mat and connected to the sense amplifier via the second switch, and a short switch arranged outside the memory mat and connected between the second and third power supply wirings. Here, in operating the sense amplifier, the short switch is made an ON state.

A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.

A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.