A semiconductor device is disclosed. The semiconductor device includes a hybrid transistor including a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a low bandgap high mobility material relative to the channel material that is high bandgap low mobility material. Memory arrays, semiconductor devices, and systems incorporating memory cells, and hybrid transistors are also disclosed, as well as related methods for forming and operating such devices.

According to one implementation of the present disclosure, a circuit comprises: a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines; and one or more canary circuits coupled to the memory array, wherein each of the canary circuits is configured to predict at least partial breakdown of a corresponding grouping of bitcells in the memory array. According to one implementation of the present disclosure, a method includes: providing an excitation stress on one or more canary circuits corresponding to a grouping of bitcells in a memory array; detecting at least a partial breakdown of the one or more canary circuits; and generating a flag.

According to one implementation of the present disclosure, a circuit comprises: a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines; and one or more canary circuits coupled to the memory array, wherein each of the canary circuits is configured to predict at least partial breakdown of a corresponding grouping of bitcells in the memory array. According to one implementation of the present disclosure, a method includes: providing an excitation stress on one or more canary circuits corresponding to a grouping of bitcells in a memory array; detecting at least a partial breakdown of the one or more canary circuits; and generating a flag.

Semiconductor devices are disclosed. A semiconductor device may include a hybrid transistor configured in a vertical orientation. The hybrid transistor may include a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a first material and the channel material includes a second, different material.

Semiconductor devices are disclosed. A semiconductor device may include a hybrid transistor configured in a vertical orientation. The hybrid transistor may include a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a first material and the channel material includes a second, different material.

Providing for a monolithic memory device comprising a combination of a one-transistor, one-resistor (1T1R) memory array, and a one-transistor, multiple-resistor (1TnR, where n is a suitable integer greater than 1) memory array is described herein. By way of example, the monolithic memory device can be a stand-alone device, configured to perform functions in response to predetermined conditions and generate an output(s), or can be a removable device that can be connected to and operable with another device. In various embodiments, the 1TnR array having high memory density can serve as storage class memory (SCM) for the monolithic memory device, and the 1T1R array having high performance and efficacy can serve as code memory. In addition to the foregoing, the 1T1R array and the 1TnR array can be fabricated from at least one common layer or a common processing step, to simplify and lower cost of fabricating disclosed memory devices.

Providing for a monolithic memory device comprising a combination of a one-transistor, one-resistor (1T1R) memory array, and a one-transistor, multiple-resistor (1TnR, where n is a suitable integer greater than 1) memory array is described herein. By way of example, the monolithic memory device can be a stand-alone device, configured to perform functions in response to predetermined conditions and generate an output(s), or can be a removable device that can be connected to and operable with another device. In various embodiments, the 1TnR array having high memory density can serve as storage class memory (SCM) for the monolithic memory device, and the 1T1R array having high performance and efficacy can serve as code memory. In addition to the foregoing, the 1T1R array and the 1TnR array can be fabricated from at least one common layer or a common processing step, to simplify and lower cost of fabricating disclosed memory devices.

An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.

An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.

A data storage device (DSD) with improved manufacturing method. The DSD includes a main printed circuit board (PCB) that includes a first PCB connector and a second PCB connector. The DSD also includes a first flash card mounted over the main PCB and including a flash memory and a flash card connector configured to connect to the first PCB connector, and a second flash card mounted over the main PCB and including a flash memory and a flash card connector configured to connect to the second PCB connector. The first flash card and the second flash card are mounted over the main PCB in a plane substantially parallel with the main PCB. The main PCB can be mounted to a base before connecting the first and second flash cards, or the first and second flash cards can be mounted to the main PCB before mounting to the base.