This application provides a memory, a chip, and a method for storing repair information of the memory. The memory includes a repair circuit that is configured to receive a first signal from a processor and determine to be powered by a first power supply or a second power supply based on a status of the first signal, to store repair information. The repair information is information of the failed bit cells in the memory. The first power supply is zero or in a high impedance state when a system is powered off, and the second power supply is not zero when the system is powered off. The memory further comprises a processing circuit configured to perform communication between the memory and the processor based on the repair information. Therefore, the repair information of the memory can be stored even during power loss.

This application provides a memory, a chip, and a method for storing repair information of the memory. The memory includes a repair circuit that is configured to receive a first signal from a processor and determine to be powered by a first power supply or a second power supply based on a status of the first signal, to store repair information. The repair information is information of the failed bit cells in the memory. The first power supply is zero or in a high impedance state when a system is powered off, and the second power supply is not zero when the system is powered off. The memory further comprises a processing circuit configured to perform communication between the memory and the processor based on the repair information. Therefore, the repair information of the memory can be stored even during power loss.

A voltage regulator and a semiconductor memory device having the same are disclosed. The voltage regulator includes an amplifier configured to amplify a difference between a reference voltage and a feedback voltage to generate an amplifier output voltage, a voltage feedback unit connected between an output supply voltage generation node and a ground voltage and configured to generate the feedback voltage, a first transfer gate unit connected between an input supply voltage and the voltage generation node and driven in response to the amplifier output voltage to provide first current, a current load replica unit connected between the voltage generation node and the ground voltage and configured to consume the first current, and a transfer unit connected between the input supply voltage and the voltage generation node and driven in response to the amplifier output voltage when the current load unit performs an operation, to provide second current.

A nonvolatile memory device comprises a first semiconductor layer including, an upper substrate, and a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction. The nonvolatile memory device comprises a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including, a lower substrate, and a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate. The second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, and the substrate control circuit overlaps at least a portion of the first through fourth regions in the third direction.

A memory device that is operable at a first voltage domain and a second voltage domain includes a memory array, a power saving mode pin and a word line level shifter circuit. The memory array operates at the first voltage domain. The power saving mode pin is configured to receive a power saving mode enable signal that is at the second voltage domain. The power saving mode enable signal is configured to enable a power saving mode of the memory device. The word line level shifter circuit is coupled to the memory array and the power saving mode pin, and is configured to clamp a word line of the memory array to a predetermined voltage level that corresponds to a first logic state during the power saving mode of the memory device.

In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

A memory device might include a controller configured to cause the memory device to generate a first sum of expected peak current magnitudes for a plurality of memory devices, and generate a second sum of expected peak current magnitudes for a subset of the plurality of memory devices, if the memory device were to initiate a next phase of an access operation in a selected operating mode; to compare the first sum to a first current demand budget for the plurality of the memory devices; to compare the second sum to a second current demand budget for the subset of memory devices; and to initiate the next phase of the access operation in the selected operating mode in response to the first sum being less than or equal to the first current demand budget and the second sum being less than or equal to the second current demand budget.

An apparatus includes a voltage regulator coupled with a first voltage source, which supplies core memory circuitry. A first transistor is coupled between an output of the voltage regulator and input/output (I/O) circuitry. A second transistor is coupled between a second voltage source and the I/O circuitry, the second voltage source to power a set of I/O buffers. Control logic coupled with gates of the first and second transistors is to perform operations including: causing the second transistor to be activated to permit current to flow from the second voltage source to the I/O circuitry; in response to detecting a current draw from the I/O circuitry that satisfies a first threshold criterion, causing the first transistor to be activated; and causing the second transistor to be deactivated over a time interval during which the I/O circuitry is powered by the first voltage source and the second voltage source.

A power generation device includes a band gap reference (BGR) circuit configured to generate a reference voltage independent of an environmental change, and a voltage generation circuit configured to transfer an input power voltage based on a sum of the reference voltage and an internal ground voltage to generate an internal power voltage.

A circuit for delaying an electric signal (CI), comprises an input for the electric signal (CI); an input for a control signal (EI); a first storage element (U5) for storing the control signal; a delay element for delaying the electric signal; and an output for the delayed electric signal (CO). According to the invention, the electric signal is delayed, based on the stored control signal. The delay circuit is employed in a fast all-digital clock frequency adaptation circuit for voltage droop tolerance.