Some embodiments include an integrated assembly having first conductive lines which extend along a first direction, and having second conductive lines over the first conductive lines and which extend along a second direction that crosses the first direction. Capacitors are over the second conductive lines. The second conductive lines are operatively proximate active structures to gatedly couple a first set of the capacitors to the first conductive lines through the active structures. Shield structures are between the first conductive lines and extend along the first direction. A voltage source is electrically coupled to the shield structures through a second set of the capacitors. Some embodiments include assemblies having two or more decks stacked one atop another.

The disclosure provides a circuit. The circuit includes a gain stage block. The gain stage block is coupled to an input voltage through a first switch. A first capacitor is coupled between the first switch and a ground terminal. A second capacitor is coupled between the first switch and a second switch. A third switch is coupled between the second capacitor and a fixed terminal of the gain stage block.

Methods of operating memory devices are disclosed. A method may include activating a first, target word line. The method may also include coupling a second word line adjacent the first, target word line to an associated first main word line while the first, target word line is activated. Further, the method may include coupling the associated main word line to a negative word line voltage while the first, target word line is activated. Associated circuits, devices, and systems are also disclosed.

To mitigate pulse shape degradation along a signal route, the signal is driven from two ends. One end of the route is loaded and the other is relatively unloaded. The loaded route and unloaded route may traverse two different metal layers on a printed circuit board. The two routes may thus be related such that the unloaded route has less RC distortion effects on the signal than does the loaded route.

A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.

A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.

A memory including current-limiting devices and methods of operating the same to prevent a spread of soft errors along rows in an array of memory cells in the memory are provided. In one embodiment, the method begins with providing a memory comprising an array of a plurality of memory cells arranged in rows and columns, wherein each of the columns is coupled to a supply voltage through one of a plurality of current-limiting devices, Next, each of the plurality of current-limiting devices are configured to limit current through each of the columns so that current through a memory cell in a row of the column due to a soft error rate event does not result in a lateral spread of soft errors to memory cells in the row in an adjacent column. Other embodiments are also provided.

A memory including current-limiting devices and methods of operating the same to prevent a spread of soft errors along rows in an array of memory cells in the memory are provided. In one embodiment, the method begins with providing a memory comprising an array of a plurality of memory cells arranged in rows and columns, wherein each of the columns is coupled to a supply voltage through one of a plurality of current-limiting devices, Next, each of the plurality of current-limiting devices are configured to limit current through each of the columns so that current through a memory cell in a row of the column due to a soft error rate event does not result in a lateral spread of soft errors to memory cells in the row in an adjacent column. Other embodiments are also provided.

An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.

A method includes, in one aspect, performing a read operation on a wordline of a memory device, wherein the wordline comprises a plurality of cells that are expected to be in a first state; based on the read operation, identifying one or more of the plurality of cells that are determined to be in a second state that differs from the first state; encoding data using information pertaining to the identified cells to generate a codeword comprising a plurality of bits to be written to the wordline, with at least one of the plurality of bits, which are to be written to at least one of the identified cells, having a value corresponding to the second state; and writing the generated codeword to the wordline