A method for fabricating a memory is provided. The method includes providing a bit-line layer, on a semiconductor substrate and having bit lines arranged in the bit-line layer; providing a shielding layer, on the bit-line layer and having a conductive shielding structure arranged in the shielding layer. The conductive shielding structure is within a top-view projection area of the bit lines and is grounded. The method further includes providing a word-line layer, on the shielding layer and having word lines arranged in the word-line layer.

A method for fabricating a memory is provided. The method includes providing a bit-line layer, on a semiconductor substrate and having bit lines arranged in the bit-line layer; providing a shielding layer, on the bit-line layer and having a conductive shielding structure arranged in the shielding layer. The conductive shielding structure is within a top-view projection area of the bit lines and is grounded. The method further includes providing a word-line layer, on the shielding layer and having word lines arranged in the word-line layer.

A semiconductor memory device includes a memory cell array, first and second pads, an interface circuit connected to the first pad and configured to transmit data input through the first pad to the memory cell array and output data received from the memory cell array through the first pad, a ZQ calibration circuit that is connected to the second pad and executes a ZQ calibration to generate a ZQ calibration value, and a sequencer configured to control the ZQ calibration circuit to apply the ZQ calibration value to the interface circuit. A command set is input through the first pad after reading data from the memory cell array to cause the interface circuit to output the data read from the memory cell array, and the ZQ calibration circuit executes the ZQ calibration after the command set is input and before the data is output through the first pad.

Methods, systems, and apparatuses for memory (e.g., DRAM) having an error check and scrub (ECS) procedure in conjunction with refresh operations are described. While a refresh operation reads the code words of a memory row, ECS procedures may be performed on some of the sensed code words. When the write portion of the refresh begins, a code word discovered to have errors may be corrected before it is written back to the memory row. The ECS procedure can be incremental across refresh operations, beginning, for example, each ECS at the code word where the pervious ECS for that row left off. The ECS procedure can include an out-of-order (OOO) procedure where ECS is performed more often for certain identified code words.

A technique includes determining, via an analog circuit, where an access rate of a memory row associated with a memory device exceeds a threshold. In various examples, upon a determination that the access rate exceeds the threshold, the technique may further comprise generating an alert to indicate possible corruption of data stored in an adjacent row to the memory row.

A technique includes determining, via an analog circuit, where an access rate of a memory row associated with a memory device exceeds a threshold. In various examples, upon a determination that the access rate exceeds the threshold, the technique may further comprise generating an alert to indicate possible corruption of data stored in an adjacent row to the memory row.

A memory system includes a memory controller, a plurality of serial data buffers, and a plurality of memory devices. The memory controller issues packetized commands and data to the serial data buffers. The serial data buffers each apply a different remapping function to remap an input command address in the packetized commands to respective remapped memory addresses that are different for each serial data buffer. The serial data buffers then issue commands to the memory devices using the remapped addresses. The remapping functions may be designed to mitigate row hammer effects. The serial data buffers may furthermore apply transformations to read and write data to facilitate encryption and decryption.

Some embodiments include an integrated assembly having digit lines supported by a base and extending along a first direction. A shield-connection-line is supported by the base and extends along the first direction. Transistor active regions are over the digit lines. Each of the active regions includes a channel region between an upper source/drain region and a lower source/drain region. The lower source/drain regions are coupled with the digit lines. Capacitors are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines extend along the second direction. The shield lines are above the digit lines and are coupled with the shield-connection-line.

Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a DBI encoder configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of high data in the read data to output global bus data for transmission through a global bus and DBI data for transmission through a DBI signal line, a DBI port being configured to receive the DBI data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the global bus data to generate output data of the DQ port; a data buffer module connected to the memory bank through the global bus; and a precharge module connected to a precharge signal line and configured to set an initial state of the global bus to Low.

An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first rows and a plurality of write assistance cells in at least one second row; a plurality of word lines respectively extending on the plurality of first rows; at least one write assistance line respectively extending on the at least one second row; and a row driver connected to the plurality of word lines and the at least one write assistance line, the row driver being configured to, during a write operation, activate at least one of the plurality of write assistance cells through the at least one write assistance line, wherein each of the plurality of write assistance cells includes the same transistor configuration as each of the plurality of memory cells and has the same footprint as each of the plurality of memory cells.