A memory includes a plurality of rows, each of which is coupled to a plurality of memory cells; a target row determining circuit suitable for determining a row that is likely to lose data among the plurality of rows as a target row; and a transfer circuit suitable for transferring, when a number of target rows determined by the target row determining circuit is equal to or greater than a threshold value, information representing that the number of target rows reaches the threshold value to a memory controller.

A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.

Embodiments of the present disclosure relate to a memory system and a memory controller, in which data input/output terminals in different data input/output terminal groups corresponding to different channels may be arranged adjacent to each other, thereby preventing skew of a signal occurring during data input/output operations and interference between different signals and reducing the cost required for implementing the memory system.

A memory device includes a memory array having a plurality of memory cells and a column decoder circuit that is configured to provide at least one column select signal for selecting corresponding bit-lines for memory operations on the plurality of memory cells. The memory device also includes a column select section that is configured to route the at least one column select signal such that non-adjacent bit-lines are exclusively selected during a same column select access memory operation.

The present disclosure relates to integrated circuits, and more particularly, to a sense amplifier circuit for current sensing in a memory structure and methods of manufacture and operation. In particular, the present disclosure relates to a circuit including: a sensing circuit including a first set of transistors, at least one data cell circuit, and a reference cell circuit; a reference voltage holding circuit comprising a second set of transistors and a bitline capacitor; and a comparator differential circuit which receives a data sensing voltage signal from the sensing circuit and a reference voltage level from the reference voltage holding circuit and outputs an output signal.

An example of an apparatus may include NAND memory and circuitry coupled to the NAND memory to control access to the NAND memory as two or more groups of memory cells, provide independent operations for the two or more groups of memory cells, share a voltage regulator among at least two of the two or more groups of memory cells, and provide a target constant voltage from the shared voltage regulator to a target group of the two or more groups of memory cells in an independent operation for the target group. Other examples are disclosed and claimed.

A computer system configured to overcome the conventional bottleneck of memory throughput. A wafer-on-wafer (WOW) technology is adapted to overcome the physical limitation of quantity and length in circuit deployments. The memory devices and the memory controllers in the logic circuit layer are improved to transmit data in differential signals. The differential signals can significantly reduce the error rate in high-speed transmissions, at a voltage level far lower than that of the conventional single-end signals. Thus, the power consumption of the computer system is significantly reduced. Furthermore, the memory controller in the computer system is improved to be an integrated controller having control over physical layer signals. Thereby, the conventional physical layer interface is no longer needed in the computer system, and therefore the cost to the computer system is further reduced.

A data storage device may include a storage including a plurality of storage regions each composed of a plurality of pages; and a controller. The controller is configured to select a plurality of target open regions from open regions among the storage regions on the basis of health information of the open regions, in each of which a programmed page and an unprogrammed page coexist, and perform control so that refresh operations for the respective target open regions are performed in a time-distributed manner.

A circuit board includes a first insulating layer; a first wiring pattern and a second wiring pattern each formed to be side to side with each other on an upper surface of the first insulating layer; a second insulating layer formed on the upper surface of the first insulating layer to cover the first and second wiring patterns; a third wiring pattern formed on an upper surface of the second insulating layer to overlap the first wiring pattern in a vertical direction; a fourth wiring pattern formed on the upper surface of the second insulating layer to overlap the second wiring pattern in the vertical direction; a first via passing through the second insulating layer and connecting the first and fourth wiring patterns; and a second via passing through the second insulating layer and connecting the second and third wiring patterns.

A sensing amplifier, coupled to at least one memory cell, includes an output terminal and a reference terminal, a multiplexer circuit, and a plurality of reference cells having equal value. An output terminal of the multiplexer circuit is coupled to the reference terminal of the sensing amplifier. Each of the reference cell is coupled to each input node of the multiplexer circuit. The multiplexer circuit is controlled by a control signal to select one of the reference cells as a selected reference cell to couple to the reference terminal of the sensing amplifier when each read operation to the at least one memory cell is performed. The plurality of reference cells are selected sequentially and repeatedly, and the one of the reference cells is selected for one read operation to the at least one memory cell.