Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.

A page buffer includes a charging circuit, first and second storage circuits, and a selection circuit. The charging circuit charges a bit line during a precharging period. The first storage circuit determines and stores data corresponding to a state of a selected memory cell among memory cells connected to the bit line while the charging circuit charges the bit line. The second storage circuit, which is a circuit separate from the first storage circuit, determines and stores data corresponding to a state of the selected memory cell after the precharging period. The selection circuit outputs a control voltage controlling a switch element connected between the bit line and the charging circuit, and determines a magnitude of the control voltage during the precharging period, based on the data stored in the first storage circuit.

A page buffer includes a charging circuit, first and second storage circuits, and a selection circuit. The charging circuit charges a bit line during a precharging period. The first storage circuit determines and stores data corresponding to a state of a selected memory cell among memory cells connected to the bit line while the charging circuit charges the bit line. The second storage circuit, which is a circuit separate from the first storage circuit, determines and stores data corresponding to a state of the selected memory cell after the precharging period. The selection circuit outputs a control voltage controlling a switch element connected between the bit line and the charging circuit, and determines a magnitude of the control voltage during the precharging period, based on the data stored in the first storage circuit.

Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to perform a sense operation on a selected memory cell of a string of series-connected memory cells, and to discharge access lines connected to the string of series-connected memory cells in a defined manner following the sense operation.

A memory is provided that includes a write multiplexer, which multiplexes among a plurality of bit line columns. The multiplexer includes a positive boost circuit that applies a positive boost to a voltage at the gates of transistors to strengthen an on state of those transistors. The positive boosting may be in addition to, or instead of, negative boosting at a write driver circuit.

A memory is provided that includes a write multiplexer, which multiplexes among a plurality of bit line columns. The multiplexer includes a positive boost circuit that applies a positive boost to a voltage at the gates of transistors to strengthen an on state of those transistors. The positive boosting may be in addition to, or instead of, negative boosting at a write driver circuit.

Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a memory array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, an activation architecture is provided using a bit cell array arranged in rows and columns to store charges that represent a weight value in a weight matrix. A read word line (RWL) may be repurposed to provide the input activation value to bit cells within a row of bit cells, while a read-bit line (RBL) is configured to receive multiplication products from bit cells arranged in a column. Some embodiments provide multiple sub-arrays or tiles of bit cell arrays.

Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a memory array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, an activation architecture is provided using a bit cell array arranged in rows and columns to store charges that represent a weight value in a weight matrix. A read word line (RWL) may be repurposed to provide the input activation value to bit cells within a row of bit cells, while a read-bit line (RBL) is configured to receive multiplication products from bit cells arranged in a column. Some embodiments provide multiple sub-arrays or tiles of bit cell arrays.

The present disclosure relates to integrated circuits, and more particularly, to a wordline system architecture supporting an erase operation and current-voltage (I-V) characterization and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: a twin cell circuit which is connected to a wordline of a memory array; a sourceline driver which is connected to a sourceline of the memory array for providing a cell level current-voltage (I-V) access of the twin cell circuit; and an integrated analog multiplexor which is connected to the twin cell circuit.

The present disclosure relates to integrated circuits, and more particularly, to a wordline system architecture supporting an erase operation and current-voltage (I-V) characterization and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: a twin cell circuit which is connected to a wordline of a memory array; a sourceline driver which is connected to a sourceline of the memory array for providing a cell level current-voltage (I-V) access of the twin cell circuit; and an integrated analog multiplexor which is connected to the twin cell circuit.