The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

The invention relates to a method for operating a memory assembly. A physical address is received. The physical address is associated with a first memory segment of a memory assembly. The physical address is modified to a modified physical address. The modified physical address is associated with a second memory segment of the memory assembly.

The invention relates to a method for operating a memory assembly. A physical address is received. The physical address is associated with a first memory segment of a memory assembly. The physical address is modified to a modified physical address. The modified physical address is associated with a second memory segment of the memory assembly.

Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

The present disclosure is directed to efficient memory activation at runtime. A memory module (e.g., a memory riser) being added to a device would typically cause the device to enter system management mode (SMM) to activate the memory module. However, activation (e.g., memory module initialization, hardware training and system reconfiguration) in SMM may substantially delay the resumption of normal operations. Consistent with the present disclosure, at least the memory module initialization and hardware training portions of the activation may be performed by an operating system (OS) in the device, allowing normal device operation to continue during the activation. The OS portion of the activation may generate configuration data. In at least one embodiment, the configuration data may be applied for use in SMM. For example, a system management interrupt (SMI) handler may apply the configuration data during a quiescent period (e.g., a period of inactivity) that occurs during SMM.

The present disclosure is directed to efficient memory activation at runtime. A memory module (e.g., a memory riser) being added to a device would typically cause the device to enter system management mode (SMM) to activate the memory module. However, activation (e.g., memory module initialization, hardware training and system reconfiguration) in SMM may substantially delay the resumption of normal operations. Consistent with the present disclosure, at least the memory module initialization and hardware training portions of the activation may be performed by an operating system (OS) in the device, allowing normal device operation to continue during the activation. The OS portion of the activation may generate configuration data. In at least one embodiment, the configuration data may be applied for use in SMM. For example, a system management interrupt (SMI) handler may apply the configuration data during a quiescent period (e.g., a period of inactivity) that occurs during SMM.

A method for efficiently waking up ferroelectric memory is provided. A wafer is formed with a plurality of first signal lines, a plurality of second signal lines, a plurality of third signal lines, and a plurality of ferroelectric memory cells that constitute a ferroelectric memory array. Each of the ferroelectric memory cells is electrically connected to one of the first signal lines, one of the second signal lines and one of the third signal lines. Voltage signals are simultaneously applied to the first signal lines, the second signal lines and the third signal lines to induce occurrence of a wake-up effect in the ferroelectric memory cells.

The present technology relates to an electronic device. According to the present technology, a memory controller may include a training controller, a training data storage, and a machine learning processor. The training controller may perform training of correcting interface signals exchanged with a memory device, generate training data that is a result of the training, and output the training data as sample training data based on a comparison result of a training reference and the training data. The training data storage may store training history information including plural pieces of sample training data. The machine learning processor may update the training reference through machine learning based on the training history information.

The present technology relates to an electronic device. According to the present technology, a memory controller may include a training controller, a training data storage, and a machine learning processor. The training controller may perform training of correcting interface signals exchanged with a memory device, generate training data that is a result of the training, and output the training data as sample training data based on a comparison result of a training reference and the training data. The training data storage may store training history information including plural pieces of sample training data. The machine learning processor may update the training reference through machine learning based on the training history information.