A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

A memory device that includes a memory array and a memory controller is introduced. The memory controller is configured to adjust a program strength of the program pulse according to the configurable ratio of the first bit value and the second bit value to generate an adjusted program pulse or to adjust a bias voltage pair according to the configurable ratio of the first bit value and the second bit value to generate an adjusted bias voltage pair. The memory controller is further configured to generate the random bit stream with the configurable ratio of the first bit value and the second bit value according to the data stored in the plurality of memory cells included in the memory array after applying the adjusted program pulse or according to the data stored in the plurality of memory cells after being biased by the adjusted bias voltage pair.

A includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to: initialize a block family associated with the memory device; initialize a timer at initialization of the block family; and aggregate temperature values received from sensor(s) of the memory device over time to generate an aggregate temperature. Responsive to programming a page residing on the memory device, the processing device associates the page with the block family. The processing device closes the block family in response to the aggregate temperature being greater than a first temperature value and the timer reaching a first time value. The processing device closes the block family in response to the aggregate temperature being less than or equal to the first temperature value and the timer reaching a second time value that is greater than the first time value.

Technologies for performing a quick reliability scan include, for a particular block of a set of blocks of different block types, each block of the set of blocks including pages of memory of a physical memory device, identifying subset of the pages of the block. The block is scanned by scanning the subset of the plurality of pages of the block for a fold condition. A page of the subset of the plurality of pages is determined to have the fold condition. After the set of blocks has been scanned, the folding of the block that includes the page that has been determined to have the fold condition is requested.

Technologies for performing a quick reliability scan include, for a particular block of a set of blocks of different block types, each block of the set of blocks including pages of memory of a physical memory device, identifying subset of the pages of the block. The block is scanned by scanning the subset of the plurality of pages of the block for a fold condition. A page of the subset of the plurality of pages is determined to have the fold condition. After the set of blocks has been scanned, the folding of the block that includes the page that has been determined to have the fold condition is requested.

A memory includes: first to N.sup.th register circuits each suitable for receiving and storing a failure address transferred from a memory controller when a corresponding selection signal of first to N.sup.th selection signals is activated, where N is an integer equal to or greater than 2; first to N.sup.th resource latch circuits suitable for storing first to N.sup.th resource signals indicating availability of the first to N.sup.th register circuits, respectively; and a priority selection circuit suitable for activating, when two or more of the first to N.sup.th resource signals are activated, one of selection signals respectively corresponding to the activated resource signals among the first to N.sup.th selection signals.

A memory includes: first to N.sup.th register circuits each suitable for receiving and storing a failure address transferred from a memory controller when a corresponding selection signal of first to N.sup.th selection signals is activated, where N is an integer equal to or greater than 2; first to N.sup.th resource latch circuits suitable for storing first to N.sup.th resource signals indicating availability of the first to N.sup.th register circuits, respectively; and a priority selection circuit suitable for activating, when two or more of the first to N.sup.th resource signals are activated, one of selection signals respectively corresponding to the activated resource signals among the first to N.sup.th selection signals.

Various implementations described herein are directed to a method. The method may receive an address to access data stored in memory. The method may enable a data access pipeline to perform memory access operations so as to access the data stored in the memory based on the address. The method may dynamically adjust the data access pipeline during the memory access operations so as to output the data based on the address.

Methods, systems, and devices for a differential write operation are described. The operations described herein may be used to alter a portion of a program file from a first state to a second state. For example, a file (e.g., a patch file) that is associated with a signature may be received at a memory device. Based on an authentication process, the file may be used to alter the program file to the second state. In some examples, the program file may be altered to the second state using a buffer of the memory device. A host system may transmit a file that includes the difference between the first state and the second state. A signature may be associated with the file and may be used to authenticate the file.

A semiconductor memory device includes a memory region from which first data and second data are sequentially read, and a data output circuit suitable for selectively performing a reset operation on a data pad according to a logical relationship between the first and second data during an output disable period between a first output enable period corresponding to first output data and a second output enable period corresponding to second output data, when sequentially outputting the first and second output data corresponding to the first and second data through the data pad.