A memory device can comprise an array of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers, and a plurality of vertical sense lines coupled to each of the plurality of tiers. The array of memory cells can further comprise a plurality of multiplexors each coupled to a respective vertical sense line and configured to electrically couple the respective vertical sense line to a horizontal sense line. The memory device can also comprise a semiconductor under the array (SuA) circuitry, comprising a plurality of sense amplifiers, each sense amplifier coupled to a respective subset of the plurality of multiplexors.

Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Two word line plates in a same plane may be activated via a shared electrode. Memory cells coupled with the two word line plates sharing the electrode, or a subset thereof, may represent a logical page for accessing memory cells. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.

Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

A memory storage apparatus including a memory circuit and a memory controller is provided. The memory circuit is configured to store data. The memory controller is coupled to the memory circuit via a data bus. The memory controller performs initial setting of the memory circuit on the basis of a width of the data bus. In addition, an operating method of a memory storage apparatus is also provided.

A memory storage apparatus including a memory circuit and a memory controller is provided. The memory circuit is configured to store data. The memory controller is coupled to the memory circuit via a data bus. The memory controller performs initial setting of the memory circuit on the basis of a width of the data bus. In addition, an operating method of a memory storage apparatus is also provided.

A memory device includes a first chip and a second chip. The first chip includes a first storage array and a second storage array. The first storage array includes at least one first storage block. The first storage block includes a plurality of first word lines extending in a first direction and a plurality of first bit lines extending in a second direction. The second storage array includes at least one second storage block. By constructing a first global bit line sub-decoder block in a first overhead projection area formed by the first storage block and constructing a second global bit line sub-decoder block in a second overhead projection area formed by the second storage block, an occupied area of the first chip and the second chip after stacking can be reduced, which reduces an occupied area of the memory device and is beneficial for minimizing the memory device.

A storage device and a manufacturing method thereof are provided and relate to the technology field of storage. The storage device includes storage a first chip and a second chip. The first chip includes a storage array. The storage array includes at least one storage block. The second chip includes a logic control circuit. The logic control circuit includes a global bit line decoder. The global bit line decoder is electrically connected to the at least one storage block. An occupied area after the first chip and the second chip are stacked can be reduced by constructing the global bit line decoder block constituted by the global bit line decoder in the top view projection area of the second chip, thereby reducing plane occupied space of the storage device. This is beneficial for minimizing the size of the storage device.